[Simh] TMXR/UC15 documentation?

[Paul Koning]

> On Jul 18, 2018, at 7:37 AM, Lars Brinkhoff <lars at nocrew.org> wrote:
> 
> Mark Pizzolato wrote:
>> Given that what you've got is one way with only the PDP11's memory
>> being accessed and no interrupts it would seem that a KA10 with a set
>> of PDP10 Unibus(s), with each connected directly to a different PDP11
>> system, you could model this pretty easily.
> 
> I will probably hook into the PDP-11 simulator.  The PDP-11 should
> accept memory read and write requests from the PDP-10.  Any guidance on
> how to do this?

You could look at Bob's PDP-15 work, but that was built for a system of coooperating processors with tight timing.  If you don't have tight timing (lockstep execution) requirements, you could use a different scheme.  For example, moving the memory to a shared memory region, and running the several simulators as separate processes that access that shared region.  Whether that's doable depends mostly on the software -- does it have interlocking operations, or does it expect to post a request to memory and have it acted on within N cycles on the sending machine?  If the latter, then you need to ensure near lock step execution of the simulators, and "just put them in separate processes" would not be good enough.

By way of analogy, the dual CPU mode of the CDC 6000 mainframes (somewhat surprisingly) doesn't require close synchronization and works perfectly well with the two CPUs running in separate threads.  On the other hand, the 10 or 20 PPUs must all run in the same thread, time-sliced on a simulated cycle basis, because they do have tight timing without sufficient explicit synchronization.

	paul