[Simh] ASTLVL

[Bob Supnik]

 From page 6-6 of DEC STD 032 (the VAX architecture spec): "Execution of 
MTPR src, #PR$_ASTLVL with src<31:0> GEQU 5 results in UNDEFINED 
behavior. The preferred implementation is to cause a reserved operand 
fault." MicroVAX II, CVAX, and Rigel all conform to the preferred 
behavior, as does the current simulator, which was written from the CVAX 
microcode. NVAX masks to 3b and does not take an exception on a value 
GEQU 5.

The 1982 Architecture Handbook describes ASTLVL as a 3b register, with 
src<31:3> ignored/read as zero, and exceptions taken on values GEQU 5. 
The780 microcode masks the input value to 3b before doing the GEQU 5 test.

So yes, the ASTLVL test needs to be model specific. I'm sending the 
overall fix and updates for CVAX and the 780 to Mark.

I suspect the behavior became undefined when MicroVAX II simplified the 
original test to save a microword. I do not see how the code fragment 
Matt references could work on a MicroVAX II, which was supported under 
4.5. Perhaps the device Matt mentions couldn't exist on a MicroVAX II?

For those who wants the gory details... uVAX, CVAX, and Rigel do an 
unsigned compare on the unmasked src and the constant 5. Carry out means 
reserved operand. Overflow is ignored. So an input of 0x80000002 - 
0x00000005 (done in the data path as 0x80000002 + 0xFFFFFFFB) generates 
overflow (ignored) and carry out.

/Bob