[Simh] [simh] new paper on improving simulator speed

[Nelson H. F. Beebe]

Although this recent paper compares new work to the QEMU simulator,
it may nevertheless offer ideas for SIMH folks:

@String{j-SIGPLAN               = "ACM SIG{\-}PLAN Notices"}

@Article{Spink:2016:EAI,
  author =       "Tom Spink and Harry Wagstaff and Bj{\"o}rn Franke",
  title =        "Efficient asynchronous interrupt handling in a
                 full-system instruction set simulator",
  journal =      j-SIGPLAN,
  volume =       "51",
  number =       "5",
  pages =        "1--10",
  month =        may,
  year =         "2016",
  CODEN =        "SINODQ",
  DOI =          "http://dx.doi.org/10.1145/2980930.2907953",
  ISSN =         "0362-1340 (print), 1523-2867 (print), 1558-1160
                 (electronic)",
  ISSN-L =       "0362-1340",
  bibdate =      "Mon Sep 5 07:32:24 MDT 2016",
  bibsource =    "http://www.math.utah.edu/pub/tex/bib/sigplan2010.bib",
  abstract =     "Instruction set simulators (ISS) have many uses in
                 embedded software and hardware development and are
                 typically based on dynamic binary translation (DBT),
                 where frequently executed regions of guest instructions
                 are compiled into host instructions using a
                 just-in-time (JIT) compiler. Full-system simulation,
                 which necessitates handling of asynchronous interrupts
                 from e.g. timers and I/O devices, complicates matters
                 as control flow is interrupted unpredictably and
                 diverted from the current region of code. In this paper
                 we present a novel scheme for handling of asynchronous
                 interrupts, which integrates seamlessly into a
                 region-based dynamic binary translator. We first show
                 that our scheme is correct, i.e. interrupt handling is
                 not deferred indefinitely, even in the presence of code
                 regions comprising control flow loops. We demonstrate
                 that our new interrupt handling scheme is efficient as
                 we minimise the number of inserted checks. Interrupt
                 handlers are also presented to the JIT compiler and
                 compiled to native code, further enhancing the
                 performance of our system. We have evaluated our scheme
                 in an ARM simulator using a region-based JIT
                 compilation strategy. We demonstrate that our solution
                 reduces the number of dynamic interrupt checks by 73\%,
                 reduces interrupt service latency by 26\% and improves
                 throughput of an I/O bound workload by 7\%, over
                 traditional per-block schemes.",
  acknowledgement = ack-nhfb,
  fjournal =     "ACM SIGPLAN Notices",
  journal-URL =  "http://portal.acm.org/browse_dl.cfm?idx=J706",
  remark =       "LCTES '16 conference proceedings.",
}

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- Nelson H. F. Beebe                    Tel: +1 801 581 5254                  -
- University of Utah                    FAX: +1 801 581 4148                  -
- Department of Mathematics, 110 LCB    Internet e-mail: beebe at math.utah.edu  -
- 155 S 1400 E RM 233                       beebe at acm.org  beebe at computer.org -
- Salt Lake City, UT 84112-0090, USA    URL: http://www.math.utah.edu/~beebe/ -
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