[Simh] pdp-11 register side effects and traps

[Don North]

Brad Parker wrote:
> Hi all,
>
> I have been running the pdp-11/34 trap diag FKABD0 on various sims and
> simulated hardware and I have a question about register side effects and
> traps.
>
> I get the impression that one of the tests in FKABD0 (103) relies on the
> fact that registers side effects, specifically post increments, don't
> happen if a bus error occurs. (or maybe I'm totally confused)
>
> Is this true of 'real hardware'?  If a bus error occurs on say
>
>    tstb (r0)+
>
> does r0 remain unincremented?
>
> It's not true in simh.  But it probably doesn't matter as I'll be no one
> relies on that behavior, other than this diag :-)
>
> I could see how the microcode could just skip over that part if a bus
> timeout occurs.
>
> -brad

The answer to this question is 'it depends'; the behavior is PDP-11 
model dependent.

The 11/94 tech manual has an all inclusive summary of the s/w apparent 
differences
between different models for lots of end-case behaviors. This particular 
case is
itemized as issue #29 on p.274 of the PDF file (see below reference). 
The behavior
of the 11/04,34,44 is to NOT increment the register; all other models DO 
increment
the register.

It could certainly be the case that SIMH does not model this peculiarity 
of the
various models correctly. It would certainly be interesting to have a 
test suite
of all the relevant diagnostics to regress SIMH functionality against to 
make sure
that SIMH is indeed model accurate. I'm not sure this is completely 
possible since
SIMH does not model timing, and some of the behaviors may be timing 
related. Most
of the functional diagnostics should probably be able to be run, however.

Don

http://bitsavers.vt100.net/pdf/dec/pdp11/1194/EK-PDP94-MG-001_Sep90.pdf