[Simh] PDP11 microstore

[Tim Shoppa]

I remember hearing from the the very outer periphery of the Mentec M1
design. Here's some comments on what "didn't seem insurmountable": "This
was by far the most complex section of the project and the phase that was
most under-estimated in the initial project plan. It was estimated that the
synthesis phase including iterative simulation and training would take 84
man days. In fact it took 264 man days."

Tim

On Mon, Jul 1, 2019 at 8:11 PM Bob Supnik <bob at supnik.org> wrote:

> The PLA scheme (another invention from the fertile mind of Bill Roberts,
> architect of the LSI11 and UDA50 proto and founder of Emulex) was
> basically a microcode and gate conservation scheme. It provided enormous
> compression for the decode phase of the PDP11 and then got exploited to
> a fare-thee-well by clever microcoders like Burt Hashizume (F11) and
> Keith Henry (J11).
>
> Sometime during the 80s, when it became clear that the process problems
> with the J11 were intractable, and it could not be shrunk for higher
> performance, I outlined a design for a single chip PDP11. Because ROM
> densities and transistor counts were so much higher by then, I felt it
> could all be done in ROM, using the usual "indirection pointers" like Rs
> and Rd for source and destination registers and a fairly simple initial
> decoding scheme to break out the interesting cases. I didn't save
> anything about it in my online archive, so I don't know what happened to
> the design notes. The idea didn't go anywhere, of course; the PDP11 was
> clearly on its last legs by then.
>
> /Bob
>
> On 7/1/2019 2:36 PM, simh-request at trailing-edge.com wrote:
> > Message: 2 Date: Mon, 1 Jul 2019 10:50:51 -0600 From: Eric Smith
> > <spacewar at gmail.com> To: simh at trailing-edge.com Subject: Re: [Simh]
> > Which PDP-11 to choose Message-ID:
> > <CAFrGgTRM4n22yugG60SLh_xT=ttk4ifAMON9rfq5FgMYz-Lh8A at mail.gmail.com>
> > Content-Type: text/plain; charset="utf-8" <snip>
> > IIRC Bob has written that no one has succeeded at building an alternate
> J11
> > hardware implementation, e.g., in an FPGA., because the microcode is not
> > entirely ROM. There is a fairly large (for the time) PLA forming part of
> > the control store. The PLA could be transformed into a ROM, but IIRC it
> has
> > _many_  inputs, so the ROM would be YUGE.
> >
> > Almost 20 years ago I wrote a program to translate the PLA into VHDL
> > directly instantiating Xilinx 4LUT primitives to see how much resources
> it
> > would consume in e.g. a Spartan 3 FPGA. I don't recall the numbers, but
> it
> > didn't seem insurmountable at the time, and with today's bigger FPGAs and
> > 6LUTs, it's even less of a problem.
> >
> > Also, I think the synthesis tools are good enough that just giving the
> PLA
> > equations to synthesis would be fine, and my scheme of programmatically
> > transforming the equations to LUT instantiations is totally unnecessary.
> >
> > Eric
>
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