[Simh] PDP11 PCLK

[Lars Brinkhoff]

Lars Brinkhoff wrote:
> The PDP-11 Dazzle Dart game sets the PCLK CSR to 115 (octal).  It
> doesn't touch any other PCLK registers.  After this, it seems to
> expect interrupts every 1/60th second.  SIMH computes the delay to be
> 1092 seconds.

My best guess is that the when the game was loaded the count buffer
register was already programmed to 1, resulting in a 1/60th delay
between inerrupts.  I updated the game source code.