[Simh] New simulator - VAX-11/782

[Sergey Oboguev]

Matt Burke <matt at 9track.net> writes:
> The sim_ipc module can provide locking for the shared memory. 
> The bit that needs working out is how to dispatch to ipc_lock for the read-interlocked memory accesses. 

Superficially looking at (AS)MP VMS code, it appears that the following should (hopefully) suffice for correct operation:

1. BBSSI and BBCCI should acquire a lock when accessing the memory location. A simplistic implementation may use one lock for the whole memory (or the whole MA780 memory bank). A more sophisticated implementation may use a bucket of locks, with a particular physical address within an MA bank mapping to a corresponding lock in the bucket (with a lock being shared by a range of MA physical addresses) -- but that would probably be an overkill for 2-CPU config which is not particularly heavy on synchronization.

1.2. VMS itself does not appear to use anything other than BBSSI and BBCCI in the ASMP code. However applications or libraries using the multiprocessing may, so for their sake the same applies to other interlocked instructions as well. Those applications or libraries might also conceivably use a higher rate of locking (justifying the bucketing of locks in this case) -- but do they even exist in the first place?

2. When sending out an IPI, the sending VCPU thread should execute a write memory barrier right before writing to the interrupt register.

3. When receiving an IPI and before handling it, the receiving VCPU thread should execute a read memory barrier matching the barrier in (2). An obvious implementation would be for (2) and (3) to acquire a lock on the "interrupt pending" register of the CPU that is the target of the IPI.

As is always with legacy MP code though, it is a bit of a gamble. Modern host processors have different cache coherency model than that of the 780 CPUs. Thus it is possible for some sequences that worked on the 11/78x multiprocessor to start failing when emulated on x86 or other contemporary host CPU. Only a detailed review of the code with respect to the cache coherency assumed by the code can tell.

But do we even know how the 780 cache operates?
Is it write-through or lazy writeback?
Do interlocked instructions (such as BBSSI/BBCCI) invalidate the 780 read cache?
Do they commit pending writebacks from the cache to MA780/main memory (MS780) before the instruction completion?
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