[Simh] DEC VT emulators on MAME

[Timothe Litt]

Since people are busy reading the schematics (which I don't have the
time to do), a brief primer on DEC schematics.  DEC std 056 (Logic
Symbology) defines how schematics are drawn.  Although it draws from
IEEE standards, there are some unique aspects that go back to the
preferences of early engineers & the resulting culture.  Later
schematics use more IEEE - but the elementary gates still use the
traditional symbols, not the IEEE rectangles.  (Very early schematics
use a unique notation, but that doesn't apply here.)

ICs use E as a refdes (IEEE uses U).  Connectors generally use J (most
others use P).  The DEC alphabet (used for connectors, esp backplanes)
omits a few letters that may cause confusion.  E.g. O.  I don't remember
the exact list.

Signal names consist of a (source) Page Function Assertion.  Page is
omitted if all uses are on the same page.  Flow is left to right/top to
bottom when possible.

The function is supposed to be meaningful; here they seem abbreviated.
(They can be multiple words, vectored, grouped/bussed, etc.)  Vectored
means a suffix of the function for the bit number or range; e.g.
Foo<15:2> L.  Bit numbering can be big or little endian depending on the
the design.   <> and [] are equivalent - SUDS and pre-CAD schematics use
[]; VALID and later use <>.

Assertion is H or L; this corresponds to the traditional Name and Name
overbar.  That is, the voltage is High or Low respecively when the sense
of the function is true.

So P1 AA15 H means a signal originating on Page 1 that is true High; P1
AA15 L is true Low.

P1 AA15 H therefore is "From Page 1, A Address bit 15, true High".  From
Kevin's research, the A probably means "processor A".

P2 BA15 H would be Page 2 B adddress bit 15, true High" - e.g. Processor B.

P2 BAD7 H is the multiplexed address/data bus of processor B; P2 BA7 H
is the demuxed Address bit 7.

VALID uses a symbol that looks like ---/O--- to match assertions.  Just
ignore it, there's nothing inside.  It allows bubble check rules to pass
when you intentionally tie a signal with one assertion to a pin with a
different assertion.  (E.g. P1 AA15H to a bubbled CS L)

Power and ground are usually implicit, but when separated (e.g. not the
default voltage or isolated) may be explicit. The VT340 schematics are
unusual in that they have a box noting power and ground pins.

Unless there are critical circuit constraints, the schematics are drawn
with an eye to logical flow; things like decoupling caps tend to be in
bulk on a separate page.  (But caps for a charge pump or oscillator
would be with their circuit since they're a "logic" function.)

A quick scan shows several PALs - they seem to be address decoding but
may also have register (e.g. bank) bits.  They'll need to be reverse
engineered.  Also note that the CPU clocks are out of phase; this
probably ties in to the dual porting of the RAM that Kevin noticed.

Finally, you may notice that unused enables tend to be tied to a 100 ohm
resistor - even to ground.  This is so bed of nails testers can
override.  Likewise, you may see MUXes from nowhere - again for testers.

I hope this helps.

On 19-Apr-17 03:05, Kevin Handy wrote:
> Looking at the schematic of the terminal
> from http://bitsavers.trailing-edge.com/pdf/dec/terminal/vt340/K-TC-VT340_Schematic_Feb87.pdf,
> it appears that there are two 8031 processors. One (E57) uses the 'P1
> AA' bus and has the 51x8 nvrom, the other (E24) uses the 'P2 BA' bus.
>
> 64Kx8 ram seems to be shared between them.
>
> 1st guess, E57 does most of the heavy work (serial, uart, keyboard,
> etc), and the other E24  handles the display.
>
> Also, for chip select,there is a 'P1 AA15 H' and a'P1 AA15 L' on the
> connector which should help with the chip selection logic. (ie. the
> inverter is inside the terminal, not on the card).
>
>

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