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<div class="moz-cite-prefix">On 29-Jul-18 06:42, Lars Brinkhoff
wrote:<br>
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<blockquote type="cite" cite="mid:7wmuuaiar8.fsf@junk.nocrew.org">
<pre wrap="">Hello,
I have a very small debugger for the GT40 called URUG, or micro RUG. It
has two troublesome instructions: CMP R3,(R3)+ and equivalent with R4.
I suppose SIMH will run it fine even though there's a hazard?
The PALX assembler complains about this, so I'm considering chaning the
code. As far as I can see, the instructions are used to add 2 to a
register. It's shorter than an ADD R3,#2, which is important because
there's not a lot of memory on this machine.
Would there be any possible downside to using TST (R3)+ instead?
The whole file is here:
<a class="moz-txt-link-freetext" href="https://github.com/PDP-10/its-vault/blob/master/files/sysen2/urug.27">https://github.com/PDP-10/its-vault/blob/master/files/sysen2/urug.27</a>
</pre>
</blockquote>
I think the 11/20 had a bug and compared C(r3)+2 to @R3; the
original intent was that it would compare C(r3) to @R3; then
increment R3. I don't recall if it was fixed in later machines.<br>
<br>
In any case, the CMP's purpose is to set the condition codes - e.g.
it does a subtract to set the condition codes, comparing the
register contents with memory. Aside from the autoincrement, it has
no other side effects.<br>
<br>
Your code doesn't use the condition codes, so there's no difference
between your cmp and a TST (R3)+.<br>
<br>
In either case, the instruction is making a memory reference. So R3
must not point at NXM (or many I/O devices, which have read
side-effects).<br>
<br>
As long as R3 points to a valid location in core memory, TST should
be fine.<br>
<br>
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