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<p>On 17-Jul-18 16:29, Lars Brinkhoff wrote:<br>
</p>
<blockquote type="cite" cite="mid:7wo9f5fvwy.fsf@junk.nocrew.org"><br>
<pre wrap="">It's mostly used to allow direct access to PDP-11 main memory.
Maybe a longer explanation is in order.
The MIT AI PDP-10 had a special device attached called the Rubin 10-11
interface. It allowed connecting up to eight PDP-11s. The interface
mapped the PDP-11 memories into the PDP-10 address space. As far as I
know (there's not much in the way of documentation), there was only
shared memory, no interrupts or any other features. The PDP-10 always
initiates accesses. The 11s could not access PDP-10 memory.
</pre>
</blockquote>
The DEC version of this is the DL10 - at least for the KA/KI. Also
supported on the<br>
KLs with external memory/IO buses. This provides a Unibus to PDP-10
memory<br>
window. IIRC, up to 4 Unibuses/DL10. Either side could write -10
memory. The<br>
DL10 connects to the IO bus (for configuration, interrupt
status/enables,<br>
etc, and the electronic finger (which triggers the boot rom - which
is how the 10 gets<br>
control for load/dump. And the memory bus for the memory references
- which to<br>
the Unibus, look like memory. We used this for ANF-10 network front
ends; some<br>
environments also connected -15s to the Unibus.<br>
<br>
You should think about what you describe as a subset of the DL10,
which someone will<br>
eventually want to add to the KA/KI emulations.<br>
<br>
For the KL10, the DTE20 uses a somewhat different architecture - I
don't have time to<br>
describe it now.<br>
<br>
I think the manuals for both are on Bitsavers - but I have a meeting
to get to...<br>
<br>
It's pretty clear that SimH needs a model/portable library for
shared memory...<br>
<br>
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