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That part is easy - the high address (and bank) bits are probably
controlled by a hardware register. Likely the lowest block (perhaps
8/16/32K) is not bank switched (so the bank switch code has a place
to live). <br>
<br>
The rest is switched by writing the desired bank into the register.
But there's also a 27256 on the terminal board, which may be the
static block. In that case, all the ROM cartridge is likely bank
switched by the register.<br>
<br>
The part Malcom needs to figure out is how the 5 hardware chips are
organized into chip selects onto the 2 address and 2 data buses that
come out from the connector. This is a separate issue from the
logical banking.<br>
<br>
There are 2 bank selects and one excess address bit. Encoded, that
would give you 8 chips. But that would require decoding hardware on
the cartridge.<br>
<br>
Without a decoder, each chip has a CE and and OE. So if a bank
select line goes directly to 2 roms' common CS, the extra address
bit can control output enable. That scheme can work for 4 ROMs.
But there are 5...<br>
<br>
So either I missed a select line on the connector, or there's a
decoder on the ROM cartridge.<br>
<br>
It's possible that the 5th ROM was a late addition (programmers
always need more code space), so an extra select line might have a
different name on the terminal control schematics. (Renaming a
signal can have all kinds of ripple effects.)<br>
<br>
Anyhow, I hope Malcom is successful.<br>
<br>
<div class="moz-cite-prefix">On 18-Apr-17 10:59, Tim Stark wrote:<br>
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<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">Ok,
I now get it. Since that it total 160K ROM space, 8031/8051
can only access 64K space with 16-bit address lines. Let’s
figure out how to access them with bank select lines and
write down which chip is on specific bank number.<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext"><o:p> </o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">Tim<o:p></o:p></span></p>
<p class="MsoNormal"><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext"><o:p> </o:p></span></p>
<div>
<div style="border:none;border-top:solid #E1E1E1
1.0pt;padding:3.0pt 0in 0in 0in">
<p class="MsoNormal"><b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">From:</span></b><span
style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:windowtext">
Simh [<a class="moz-txt-link-freetext" href="mailto:simh-bounces@trailing-edge.com">mailto:simh-bounces@trailing-edge.com</a>] <b>On
Behalf Of </b>Timothe Litt<br>
<b>Sent:</b> Tuesday, April 18, 2017 10:42 AM<br>
<b>To:</b> <a class="moz-txt-link-abbreviated" href="mailto:simh@trailing-edge.com">simh@trailing-edge.com</a><br>
<b>Subject:</b> Re: [Simh] DEC VT emulators on MAME<o:p></o:p></span></p>
</div>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal" style="margin-bottom:12.0pt">You can remove
the ROMs (EPROMS) nondestructively with hot air. But an
easier approach would be to tack some wires onto the connector
& wire them to a 28 pin DIP header. Then your existing
programmer can read them.<br>
<br>
The schematics don't seem to contain the ROM module, but one
can infer a lot from the connector.<br>
<br>
It looks like there are 2 banks of ROMs on the cartridge;
there are also 2 select lines. Address bits go to A15; the
27c256 uses a0-a14.<br>
<br>
So there are probably 2 chips on one bank, 3 on the other.
Since they don't write the EPROMs (they'e windowless, so OTP),
they probably use A15 for OE and the bank lines for CS. It's
not obvious how the 5th chip is selected - perhaps there is a
decoder on the card. A couple of NAND gates, or perhaps a
decoder to decode the 2 bank selects? I didn't backtrack
through the schematics to find out how the selects are
generated.<br>
<br>
In any case, some time with an ohmmeter should let you figure
it out. At worst you'd need 2 headers (1/bank), but most ROM
programmers have strong drivers (address), and even 5 chips in
parallel should be OK for the data bus. So you can probably
get by with 1, and some jumpers (or a dipswitch) to set
A15/the BS for dumping each one.<br>
<br>
DEC ROMs should have a checksum (or more likely, CRC), so you
can verify that you dumped them correctly. This would usually
be in the last byte(s) of each chip - except where booting
starts at the highest address. (E.g. some Intel CPUs). Then
look at the beginning :-)<br>
<br>
Have fun.<br>
<br>
<o:p></o:p></p>
<div>
<p class="MsoNormal">On 18-Apr-17 09:25, <a
moz-do-not-send="true"
href="mailto:malcolm@avitech.com.au">malcolm@avitech.com.au</a>
wrote:<o:p></o:p></p>
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<pre>Just a quick update: I've broken open the VT340 ROM cartridge. Inside are 5 x surface-mount N27C256 ROMs.<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>Some pictures of the ROM cartridge are now included on this page -> <a moz-do-not-send="true" href="http://avitech.com.au/?p=1818">http://avitech.com.au/?p=1818</a> <o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>Is there anyone who has the tools, time and interest to remove these ROMs and dump the contents? If so, please let me know and I will pay the cost of shipping to get this cartridge to you.<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>Malcolm.<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre><o:p> </o:p></pre>
<pre>_______________________________________________<o:p></o:p></pre>
<pre>Simh mailing list<o:p></o:p></pre>
<pre><a moz-do-not-send="true" href="mailto:Simh@trailing-edge.com">Simh@trailing-edge.com</a><o:p></o:p></pre>
<pre><a moz-do-not-send="true" href="http://mailman.trailing-edge.com/mailman/listinfo/simh">http://mailman.trailing-edge.com/mailman/listinfo/simh</a><o:p></o:p></pre>
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<p class="MsoNormal"><o:p> </o:p></p>
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