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I have a low-level pdp-11 question...<br>
<br>
I'm confused about writing to the PSW on cpu's which support user
& supervisor mode. My <br>
read of the docs is that in user mode you should not be able to
write the "mode" bits of the PSW.<br>
<br>
(or, perhaps more accurately, you should not be able to *clear* any
mode bits from user space)<br>
<br>
I have a little diagnostic which doesn't work as I though it should
under simh and I thought I'd<br>
ask what others think...<br>
<br>
Basically, simh allows code running in "user mode" to write the PSW
even when (I claim) it<br>
should not. I have not tried this on a real 11/44 or 11/34 yet,
but I can/will.<br>
<br>
Should simh allow this? In the test blow the "clr @#PSW" is
successful when run<br>
on simh and I think it should basically be a nop...<br>
<br>
(which begs another question - should it be a nop? or a exception?)<br>
<br>
A side question might be "the psw is not protected from writes,
except by using<br>
the mmu" - is this true on all models? or just some? The 11/40
manual implies<br>
that it *is* protected. But 11/73 docs seem to say the opposite and
imply using the mmu.<br>
<br>
diagnostic follows:<br>
<font face="Courier New, Courier, monospace"><br>
.TITLE test17<br>
.ASECT<br>
PSW=177776 ;processor status word<br>
.=34<br>
.word 200<br>
.word 0007<br>
.=200<br>
mov #200, r5 ;we should be in kernel mode here<br>
rti<br>
.=500<br>
clr @#PSW ;kernel mode <br>
mov #500,sp ;sp=500 in kernel mode<br>
mov #140000,@#PSW ;user mode <br>
mov #700,sp ;sp=700 in user mode<br>
trap 377 ;should move us to kernel mode<br>
nop<br>
clr @#PSW ;back to kernel mode <br>
nop<br>
halt<br>
<br>
</font><br>
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