[Simh] Is it possible to simulate the first Vaxen I ever used?

[Tim Shoppa]

BTW... great interview of Richie Lary:
https://www.youtube.com/watch?v=lp2NSbJ2H1k

On Mon, Mar 23, 2020 at 2:36 PM Paul Koning <paulkoning at comcast.net> wrote:

>
>
> > On Mar 23, 2020, at 1:29 PM, Timothe Litt <litt at ieee.org> wrote:
> >
> > ...
> >> Since the KL10 was DEC's biggest, most expensive machine at the time,
> it wasn't nearly as cost sensitive as their other CPUs, so there probably
> wasn't even any consideration given to using PROM for the control store.
> > I don't think you could have found fast enough PROMs.  The KL is an ECL
> machine.  The RAMs are ECL, and the timing is hairy enough that the modules
> are only populated 1/2 way back - to fill the board would break timing.
> The boards also have loops of etch that serve as delay lines.
> Manufacturing would short the loops at the right place for each board -
> depending on how the board (and RAMs) turned out.  Today we take for
> granted process controls and tolerances that were, if not unattainable,
> unaffordable at that time.
>
> Was there such a thing as ECL ROM?  I don't remember.
>
> It's interesting to watch the evolution of high speed computers.  There's
> a continuous back and forth between memory and logic, depending on where
> the limitations are in the year or two when the design was frozen.  RAM and
> ROM have generally been different.
>
> One example that comes to mind is the character stroke generator for the
> CDC 6000 series mainframes.  That has a 10 MHz waveform step clock, so it
> needs a ROM with an access time comfortably below 100 ns (unless you want
> to use multiple banks).  In 1964 that was problematic, and the 6000 series
> display controller instead uses a massive logic chain to produce all the
> waveform data for all the character codes.  5-ish years later, in the Cyber
> 170 series, all that was replaced by a ROM.  Same data, but one chip
> instead of 100 or so plug-in logic modules.
>
> Another example, also from that machine: the memory access and scheduling
> machinery is quite complex, with 32 memory banks operating concurrently.
> That's because many of the instructions complete in far less than a memory
> cycle time: 300 or 400 ns for the simpler instructions, and even a multiply
> takes only 1000 ns, while memory cycles in 1000 ns.  By 1964 standards,
> 1000 ns was amazingly fast, I don't think anyone else came close, and the
> core memory wiring and circuitry is quite exotic to make it go so fast.
>
> On the VAX 730: as far as I'm aware it's the only VAX built out of
> standard LSI CPU components.  The guts of the CPU is AMD 2901 bit-slice
> chips.  All other DEC microprogrammed machines I can think of had their own
> purpose-designed logic.
>
> 2901 bitslices do appear in other DEC products, the UDA comes to mind.
> And that has, for running on-board diagnostic tools, a small PDP11-like
> instruction set implemented in a little bit of 2901 microcode.  By Richie
> Lary, wizard of compact software...
>
>         paul
>
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