[Simh] Is it possible to simulate the first Vaxen I ever used?

[Eric Smith]

On Mon, Mar 23, 2020 at 7:34 AM Robert Armstrong <bob at jfcl.com> wrote:

> The 730 was interesting in that ALL of the CPU microcode was in RAM and
> was loaded by the CFE at boot time.  It was possible to locally modify the
> 730 microcode, and DEC even had a set of microcode development tools for
> the 730.  I've never seen them except in references.
>

The 11/785 and 8600/8650 also used RAM for the entire control store, loaded
by the front end. The 11/785 front end was a PDP-11/03, like the 11/780,
but on the 11/780 the front end only had to load the patch store, not the
entire microcode.

Fast static RAM was considerably more expensive per bit than PROM in the
1970s and early 1980s. As the price of fast static RAM came down in the
1980s, the trend was to use entirely RAM control store, but later in the
1980s as they developed single-chip CPUs, it once again became impractical
to use all-RAM control store. RAM bits require approximately six times the
die area per bit as masked ROM. That drove the microprocessors to use
mostly ROM, with a small RAM patch area, just like the 11/780.

The first two DEC machine to use entirely RAM control store were the KL10
and KS10 36-bit PDP-10 CPUs, in 1975 and 1978, both used in DECsystem-10
and DECSYSTEM-20 systems. The KL10 was the biggest and most expensive
PDP-10, and the KS10 was the smallest and least expensive.  The earlier
36-bit CPUs, the 166 (PDP-6), KA10, and KI10, were hardwired rather than
microcoded.

Since the KL10 was DEC's biggest, most expensive machine at the time, it
wasn't nearly as cost sensitive as their other CPUs, so there probably
wasn't even any consideration given to using PROM for the control store.

The decision to use RAM control store on the KS10 is less obvious. It was
still an expensive machine, maybe 20% or 25% of the cost of a KL10, so it
may still have not been considered cost sensitive, and the benefits of easy
microcode updates may have been considered more important than they would
have been on e.g. the PDP-11 CPUs.

The KS10 control store RAM has parity, and RAM parity errors were
apparently fairly common. A control store parity error would halt the CPU
and interrupt the 8085 front end, which would reload the control store and
restart the machine. DEC patented that.
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