[Simh] DLI losing upper bit

[Mark Pizzolato]

On Thursday, June 25, 2020 at 8:42 AM, Paul Koning wrote:
> > On Jun 25, 2020, at 11:07 AM, Mark Pizzolato wrote:
> >
> > On Thursday, June 25, 2020 at 7:28 AM, Paul Koning wrote:
> >> I'm trying to use a SIMH PDP11 "DLI" device for DDCMP.  That requires 8 bit
> >> transparent data, of course.  It's not working.
> >>
> >> A trace shows that the simulator is stripping the upper bit on received
> bytes.
> >> The console has a command to tell it not to do that (set tti 8b).  But while
> there
> >> is "set dlo 8b" there is no "set dli 8b".
> >>
> >> Is there a way to get DLI not to corrupt data?
> >
> >      sim> SET DLOn 8B
> >
> > Affects BOTH input and output traffic mode for line 'n' on the MUX.
> >
> >      sim> SET DLO 8B
> >
> > is ONLY equivalent to:
> >
> >      sim> SET DLO0 8B
> >
> > This is illustrated by HELP DLO SET
> >
> > - Mark
> 
> Thanks, I see it does.  The help doesn't actually say that it affects both sides,
> and since for TT there are separate commands it would be nice to say it
> explicitly.

What's there now is more thorough and you now must specify DLO0 vs 
either DLO0 or DLO when setting line 0 modes.

- Mark