[Simh] Design considerations in the J11

[Bob Supnik]

The J11 was started in mid 1979, in the subsection of Small Systems 
Engineering (the low-end PDP11 group) that handled microprocessor 
design. In the prior six months, I had been working as a systems 
analyst/product strategist in SSE and moonlighting as a microprogrammer 
on the F11 CIS option. I wrote a strategy paper recommending two 
projects: a 32b VLSI VAX and one last PDP11 microprocessor. Both 
recommendations were accepted. The 32b VLSI project was Scorpio (V11), 
and the PDP11 project was J11.

J11 was intended to converge the three different lines of PDP11 
development that had emerged in the early and mid 70s:

- Low end systems (11/05 -> LSI11 -> F11)
- Mid range systems (11/40 -> 11/34 -> 11/44)
- High end systems (11/45 -> 11/70)

It would be the logical successor to the LSI11 and F11 in the Qbus board 
and systems space, but it would have the performance and features of the 
high-end processors, including the never-shipped MPs.

This led to the basic requirements:

- 11/70 feature set (two general register sets, three modes, PIRQ, cache 
support, I and D space), plus more recent add-ons, like CSM and 
interlocking ASRB.
- 11/70 class performance, by running at 5Mhz (200ns cycle time).
- Integral and accelerated floating point.
- CIS option.

Some features were dropped, like the trapping (as opposed to faulting) 
memory management modes; they were not used by RSTS/E or RSX11M+. And an 
opportunity was missed: to use bits in the PDR to increase physical 
memory space beyond 4MB.

By the time J11 finally shipped in 1983, the "all-in on VAX" strategy, 
promulgated by Gordon Bell before he left, was in full swing, and 
further technology investments in PDP11 CPUs were discouraged. 
Accordingly, the CIS option was dropped, as was any thought of a 
successor product. Dom LaCava and Jesse Lipcon spun variants on J11 
through the end of the 80s and made the PDP11 group one of the most 
profitable in DEC. In the 90s, Mentec created a PDP11 CPU (M11) using 
off-the-shelf VLSI parts, and then reimplemented it as an ASIC (M1).

A couple of anecdotes:

- In order to have a "CAD forward" strategy, with tools replacing paper 
design, I asked Dick Clayton, the responsible VP, for a dedicated KS10 
(1/3 of a mip!) for the project. He thought this was totally outrageous 
- a dedicated time-sharing system for just one team! - but eventually 
authorized the acquisition.
- The Harris team had no experience with high-speed design and some its 
issues, such as metastability. The first schematics were filled with 
hazards. The chief Harris circuit designer was summoned to Hudson MA, 
and Bob Stewart - who had discovered and fixed the metastability issues 
in the 11/45 - patiently taught a multi-hour tutorial on metastability 
and the need for stacked flip-flops. The Harris designer kept proposing 
workarounds, and Bob patiently analyzed the results and showed that the 
hazard has simply been moved somewhere else.
- Interconnect verification (IV) on the T11 had taken months of tedious 
hand labor, and it was only 17,000 transistor sites. The J11 was much 
larger. Accordingly, the J11 team hired a small army of summer students 
to create a machine-readable netlist from the paper circuit schematics 
and used the KS10 to do computer based IV - a first for DEC.

/Bob Supnik