[Simh] pdp11 fails MAINDEC CPU test 14 D0NA

[Paul Koning]

> On Jul 9, 2020, at 8:29 PM, Johnny Billquist <bqt at softjar.se> wrote:
> 
> On 2020-07-10 02:19, Paul Koning wrote:
>> The VAX architecture seems to have been an explicit design effort.  For the Alpha this was even more obvious, where a monstrously large book (certainly 500 pages, maybe double that) was written and reviewed in depth before anything was cast into silicon.  Not so for the PDP11, as you pointed out.
> 
> It definitely was an explicit effort. I seem to remember seeing/reading somewhere at some point that this was because of what had happened on the PDP-11. So a lesson learned kind of thing.

At least DEC learned.  Too many other companies had the same opportunity but did not take it.

> I used to have an Alpha Architecture manual, but I lost it somewhere along the way. :-(

That's pretty amazing.  I had one, but I had to give it back.  It was a restricted access numbered copy.

> ...
>> My suspicion is that the PDP-11 architecture handbook was an after the fact effort.  The date (1983) supports that notion.  Also, it's a handbook, a fat paperback like the processor and peripheral handbooks.  I don't know of any internal analog, like DEC Std 032 for VAX.
> 
> Yeah, I would expect that it would an after the fact thing. But it would still be interesting to see any effort made by DEC to put it all in one book. As mentioned, the list (maybe in different revisions) do exist in multiple other handbooks and manuals. But then it's just an appendix without much further analysis.
> 
> I think I also saw/read somewhere that different new PDP-11 implementations basically tried to look at what had previously been done, and tried to just match that, as there was no official definition of a PDP-11. But then they always did some deviation or other for the sake of efficiency, cost or just clean up.

I think at least one or two differences were deliberate and planned -- between 11/20 and the rest.  That's what the existence of the "Z" error code in the assembler implies.  (I think that pops up if you do one of those R0,(R0)+ instructions or cases like that, where the whole thread started.)  And the change of RTI along with the introduction of RTT is clearly an intentional change for optimization.

	paul