[Simh] More on DMA to IO page

[Eric Smith]

On Thu, Sep 6, 2018 at 4:12 PM, Johnny Billquist <bqt at softjar.se> wrote:

> The problem is that the MK11 memory boxes also have CSRs, and those are
> living in that last 8K space. If you have memory mapping those same
> addresses, I have no idea what happens, but either way is not good.

Either you have the memory, in which case the CSRs are unaccessible, and
> they control how the memory box works. Or else you have the CS‰s, but what
> then happens to those memory cells?
>

You're right. The Unibus does not go to the MK11, which only connects via
the memory bus to the KB11-C cache, so at least some I/O page accesses have
to go across the memory bus for the MK11 CSRs. Rather than decoding and
only sending the specific MK11 CSR I/O page accesses to the memory page,
the KB11-C cache system most likely just sends all I/O page accesses to
both Unibus and the memory bus, expecting only one to acknowledge.

If I was desperate to have 4088KB/2044KW, I could probably kludge up
additional logic to the MK11 control modules to explicitly disable the RAM
operation for the entire I/O page range. However, I have only ten M8722
modules (2.5MB/1.25MW), so it isn't something I actually need.
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