[Simh] CMP R3,(R3)+

[Paul Koning]

> On Jul 29, 2018, at 4:42 PM, Timothe Litt <litt at ieee.org> wrote:
> 
> 
> On 29-Jul-18 06:42, Lars Brinkhoff wrote:
>> Hello,
>> 
>> I have a very small debugger for the GT40 called URUG, or micro RUG.  It
>> has two troublesome instructions: CMP R3,(R3)+ and equivalent with R4.
>> I suppose SIMH will run it fine even though there's a hazard?

Not exactly a hazard, but a documented incompatibility among implementations.  In fact, there exists code that does something very similar to tell an 11/20 from others:

	CMP	PC,#.+4		;SEE WHEN PC GETS INCREMENTED
	BEQ	O.ST01		;IS IS A 11/20, ...

>> 
>> The PALX assembler complains about this, so I'm considering chaning the
>> code.  As far as I can see, the instructions are used to add 2 to a
>> register.  It's shorter than an ADD R3,#2, which is important because
>> there's not a lot of memory on this machine.
>> 
>> Would there be any possible downside to using TST (R3)+ instead?

Yes, that is the standard way to do this.  I have never seen the code you quoted before and I can't imagine any reason for doing that.

Either option of course only works if R3 contains a valid memory address, and it must be even.  A short way to increment by 2 that doesn't depend on R3 being even would be CMPB (R3)+,(R3)+.

It's fairly common to see the TST, not just because it's shorter, but also because it has a well known effect on the C condition code (it clears it).  For example, a common pattern when C is used to indicate success/fail in a subroutine:

	TST  (PC)+     ; Indicate success
fail:   SEC
	MOV  (SP)+,R1  ; ...
        RTS  PC

You might also see code that pops a no longer needed value from the stack, either clearing or setting C or leaving it alone.  To clear, you'd see TST (SP)+.  To set, COM (SP)+.  To leave it untouched, INC (SP)+.  (More obscure is NEG, which sets C if the operand is non-zero and clears it if it is zero.)

	paul