[Simh] VAX 8200 field manuals
mitch wright
mitch.wright2012 at gmail.com
Sun Mar 19 10:01:53 EDT 2017
Someone sent me these many years back, don't recall who.
Also, If I recall correctly, all of the production versions of the
8200/8300 microcode was published in the "RED" field maintenance microfich.
The computer history museum or Al should have it packed away some where.
Regards, Mitch
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PPPPPP A RRRRRR TTTTTTTTT IIIII IIIII
P P A A R R T I I
P P A A R R T I I
P P A A R R T I I
P P A A R R T I I
PPPPPP AAAAAAA RRRRRR T I I
P A A R R T I I
P A A R R T I I
P A A R R T I I
P A A R R T IIIII IIIII
USER AND PROGRAMMING INFORMATION
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 2
PART II TABLE OF CONTENTS 24 Jan 86
1.0 POWERUP FLOW . . . . . . . . . . . . . . . . . . . . 3
2.0 MICROCODE PATCHES . . . . . . . . . . . . . . . . . 4
2.1 PATCH MECHANISM . . . . . . . . . . . . . . . . . 4
2.2 READING PATCHES FROM THE ROM/RAM CHIPS . . . . . . 6
2.3 LOADING PATCHES . . . . . . . . . . . . . . . . . 7
3.0 SELFTEST . . . . . . . . . . . . . . . . . . . . . 10
3.1 SELFTEST DISCRIPTION . . . . . . . . . . . . . . 10
3.2 SELFTEST USERS AND USES . . . . . . . . . . . . 11
3.3 SELFTEST PERFORMANCE GOALS . . . . . . . . . . . 11
3.4 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . 12
3.5 POWERUP AND SELFTEST FLOW DIAGRAM . . . . . . . 19
4.0 INITIALIZATION . . . . . . . . . . . . . . . . . . 20
4.1 POWER UP INITIALIZATION . . . . . . . . . . . . 20
4.2 PROCESSOR INITIALIZATION . . . . . . . . . . . 21
4.3 SYSTEM BUS INITIALIZATION . . . . . . . . . . . 23
5.0 BOOTING . . . . . . . . . . . . . . . . . . . . . 28
5.1 BOOT MICROCODE . . . . . . . . . . . . . . . . . 28
6.0 EEPROM CONTENTS . . . . . . . . . . . . . . . . . 32
6.1 CHECKSUM ALGORITHM FOR EEPROM DATA . . . . . . . 38
6.2 READING AND WRITING THE EEPROM . . . . . . . . . 38
7.0 CONSOLE . . . . . . . . . . . . . . . . . . . . . 39
7.1 CONSOLE SOURCES . . . . . . . . . . . . . . . . 39
7.2 CONSOLE I/O MODE ENTRY . . . . . . . . . . . . . 44
7.3 SCORPIO CONSOLE COMMANDS AND SYNTAX . . . . . . 45
7.4 APT SUPPORT . . . . . . . . . . . . . . . . . . 64
7.5 CONSOLE OUTPUT DURING BOOTING . . . . . . . . . 64
8.0 MACHINE CHECK SPECIFICATION . . . . . . . . . . . 68
8.1 MACHINE CHECK CONDITIONS . . . . . . . . . . . . 69
8.2 MACHINE CHECK EXCEPTION . . . . . . . . . . . . 71
8.3 ERROR RECOVERY . . . . . . . . . . . . . . . . . 72
8.4 STACK CONTENTS DURING MACHINE CHECK . . . . . . 73
9.0 SYSTEM CONTROL BLOCK VECTORS . . . . . . . . . . . 79
10.0 PCNTL CSR . . . . . . . . . . . . . . . . . . . . 81
11.0 SERIAL LINES . . . . . . . . . . . . . . . . . . . 93
11.1 RXCS1, RXCS2, RXCS3 - RECEIVE CSR REGISTERS . . 93
11.2 RXDB1, RXDB2, RXDB3 - RECEIVE DATA REGISTERS . . 95
11.3 TXCS1, TXCS2, TXCS3 - TRANSMIT CSR REGISTERS . . 96
11.4 TXDB1, TXDB2, TXDB3 - TRANSMIT DATA REGISTERS . 98
12.0 BI PROGRAMMING . . . . . . . . . . . . . . . . . . 100
12.1 BI RESET . . . . . . . . . . . . . . . . . . . . 100
12.2 BI STOP COMMAND . . . . . . . . . . . . . . . . 100
12.3 BIIC REGISTERS . . . . . . . . . . . . . . . . 100
13.0 PROGRAMMING THE WATCH CHIP . . . . . . . . . . . . 114
13.1 CSR DEFINITIONS . . . . . . . . . . . . . . . . 116
13.2 OPERATING SYSTEM SOFTWARE . . . . . . . . . . . 118
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 3
POWERUP FLOW 24 Jan 86
1.0 POWERUP FLOW
The flow diagram in fig. 1.0 shows the flow of the KA820 powerup
microcode. This flow diagram should be consulted when reading sections 2
through 5.
figure 1.0 POWERUP MICROCODE FLOW
.----------------------------.
+---------------------------------->| DCLO deasserted. |
| | BI selftest initiated. |
| | yellow LED off, red LED on.|
| | | baud rate to 1200 on UART0 |
| | `-----------+----------------'
| | |<-------------------------------.
| | V | NO
| | .-----------+-----------. NO .-------------------------.
| | | ACLO deasserted ? |---------->| ACLO 10 sec. timeout? |
| | `-----------+-----------' `-------------------------'
| | | Y | YES
| | V <-------------. V
| | .------------------. N .-----------+-----------. | .----------------------.
| | | can't read valid |<-----------| Able to set baud rate | | | Print ?41 to console |<---------.
| | | baudrate (30-37) | | from EEPROM? | | `----------+-----------' |
| | `--------+---------' `-----------+-----------' | |<------------------. |
| | | | Y | V | |
| | V | | Y .--------------------. | |
| | .-----------------. V `------+ ACLO deasserted? | | |
| | | set default BR | .-----------+------------. `---------+----------' | |
| | | to 1200 | | Print ASCII "#". | | NO | |
| | `-----------------' | Init CAM and RAM of CS.| | | |
| | | | Read eeprom constants. | V | |
| | | | Checksum eeprom | .---------------------. N | |
| | V | patch section. | | 20 minute timeout? +------' |
| | .<-------------------------+ Load patches, r/wcheck | `--------+------------' |
| | | <--any failures | & enable patches. | | Y |
| | | | Turn red LED off. | `----------------------'
| | | `-----------+------------'
| | |
| | V
| | .-----------+-----------.
| | .<--+ T(est) command? |
| | | Y `-----------+-----------'
| | | | N
| | | V
| | | .-----------+-----------.
| | |<--+ Fast or Slow test ? +---.
| | | S `-----------------------' F |
| | | |
| | V V
| | .-----------+-----------. .-----------+-----------.
| | | Comprehensive Slow | | Fast Test. |
| | | Test. Print ASCII | | Enable Cache and |
| |<---------+ character after | | F Chip if present. |
| | failures | each section. | `-----------+-----------'
| | `-----------+-----------' |
| | | |
| | `---------------+---------------'
| | |
| | V
| | .---------------------------------.
| | | Print ASCII "#". |
| | | Do Power Up Init. |
| | | | Light yellow LED, clr Broke bit |
| | `----------------+----------------'
| | |
| | V
| | .-----------+-----------.
| | | Processor Init. |
| | | load PCNTL enable |
| | | for RX50 from EEPROM |
| | | Init state, PSL, |
| | | M Chip parity, |
| | | Istatus, etc. |
| | `-----------+-----------'
| | |
| | V
| | .--------------+-------------.
| | | System Init. |
| | | Read BI BROKE bits, if |
| | | broke, set warm flag. |
| | | | Output BI sys stat to cnsl.|
| .-----+-----. | .-----------------. | Set BI memory S/E adrs's. |
| | Save state| | | Processor Init | `--------------+-------------'
| | T command.| | | I command. | |
| `-----+-----' | `-----+-----+-----' |<---------------------------------------------------------.
| ^ | ^ | | |
| | V | V W/C=11, T, V |
| .-+--------+--------+-----+-. or halt .-----------+-----------. W/C=00 .-----------------------. |
| | VAX Console mode. +<--------+ Boot decision ? +------------->+ Set WARM flag. | |
| `-+---+-------------+-------' `-----------+-----------' `-----------+-----------' |
| | ^ V W/C=10, | | |
| | | .------+------. and DCLO | V |
| | | | B command. | boot | .-----------+-----------. |
| | `------+------' |<-------------------------+ Restart Param. Block? | |
| | | | N `-----------+-----------' |
| | V | | Y |
| | .------+------. | | |
| | | System Init +--------------------->| | |
| | `-------------' | | |
| | V V |
| | .-----------+-----------. .-----------+-----------. |
| | | Set COLD flag. | | Load PC with 2nd | |
| +<------------------------------+ Find 64K good memory. | | longword of RPB. | |
| | failure | Load PC with address | `-----------+-----------' |
| | | of boot device. | | |
| | `-----------+-----------' | |
| | | | |
| | |<-------------------------------------' |
| | V |
| | .-----------+-----------. |
| | | Processor Init. | |
| | | Start at PC, either | |
| | | boot or restart. | |
| | `-----------+-----------' |
| | | |
| | V |
| | ^P and NEXT halts. .-----------+-----------. VAX error halt .-----------------------. |
| `-------------------------------+ VAX program mode. +--------------->| Set halt code. +-----'
`---------------------------------->| run light on. | or halt instr `-----------------------'
START, CONTINUE, NEXT commands. `-----------------------'
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 4
MICROCODE PATCHES 24 Jan 86
2.0 MICROCODE PATCHES
2.1 PATCH MECHANISM
| Microcode changes can be incorporated by patches which are stored in the
| EEPROM. Their purpose is to correct microcode bugs; they are not meant
| for customizing the microcode. The patches are loaded after powerup from
| the EEPROM by microcode. They can also be loaded by VAX MTPR
| instructions. Microcode loads the patches from the EEPROM upon the
| deassertion of DCLO L.
Patches are loaded into the custom VLSI RAM/ROM control store chips as
described in the hardware section. The Control store consists of the
following parts:
15K locations of 40-bit ROM-based microwords.
(addresses 0 - 3BFF)
1020 locations of 40-bit RAM-based microwords
(addresses 3C00 - 3FFB)
160 locations of 14-bit CAM (content addressable memory).
An empty CAM location is loaded with the ROM address to be patched. The
patch for the ROM address is loaded into RAM at the address (3C00 HEX +
ROM address<9:0>). When a ROM-based microinstruction is fetched from the
controlstore, its address is compared against all 160 locations of the
CAM. If the micro address is in the CAM, the microinstruction at RAM
location (3C00 HEX + ROM address<9:0>) is substituted for the ROM
instruction.
For example:
ROM location 1200 HEX is to be patched.
To do this:
An empty CAM location is loaded with 1200 HEX
RAM location 3E00 HEX is loaded with the 40-bit
microinstruction patch.
Thus when microinstruction at ROM location 1200 HEX is to be executed,
the microsequencer substitutes the RAM instruction at location 3E00 hex
in its place.
The following example describes a multiple instruction patch:
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 5
MICROCODE PATCHES 24 Jan 86
What is loaded into the ROM/RAM chips:
Empty CAM location loaded with patched ROM address 2256.
RAM location 3E56 <-- 1st instruction of patch (branch to 3E33).
RAM location 3E33 <-- 2nd instruction of patch
The execution flow if ROM location 2256 is patched:
ROM location 2256 is fetched but NOT executed. (patched with 3E56)
RAM location 3E56 is fetched and executed. (does jump to 3E33)
RAM location 3E33 is fetched and executed. (jump back to ROM 2252)
ROM location 2252 is fetched and executed. (goes somewhere)
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 6
MICROCODE PATCHES 24 Jan 86
2.2 READING PATCHES FROM THE ROM/RAM CHIPS
The following two privileged processor registers are used for examining
the contents of the patch RAM using MTPR and MFPR instructions.
WCSA IPR #2C
31 22 21 08 07 00
| +----------------------+--------------------------+------------------+
| | | Address bits <0:13> | data bits <16:9> |
| +----------------------+--------------------------+------------------+
This register is used in conjunction with the WCSD register for reading
the contents of the control store. It is interpreted by microcode which
then accesses the ROM/RAM chips as specified by the 14 bit address. The
low order byte contains bits <16:9> of the 40 bit microword that is to be
read; the other 32 bits of data are read using the WCSD register.
NOTE: The 14 address bits are BACKWARDS from the normal VAX order, and
the data bits that are read in the WCSD register are permuted in an
unusual way which reduces the amount of microcode required.
WCSD IPR #2D
31 23 22 21 00
+---------------+----+-----------------------------------------------+
|data bits <8:0>|<39>| data bits <17:38> |
+---------------+----+-----------------------------------------------+
To READ a control store location, an MTPR is first performed to the WCSA
with a valid address and don't care data. Then an MFPR is performed from
the WCSD followed by another MFPR from the WCSA, IN THAT ORDER. No
interrupts or context changes should be taken within this
three-instruction sequence, or the internal address/data state may be
lost. Addresses 0000 to 3BFF refer to ROM locations. Addresses 3C00 to
3FFB refer to patch RAM locations. Addresses 3FFC to 3FFF refer to the
CAM match register. When reading a ROM location that has been patched,
the data returned is the patch, NOT the original ROM word.
To read patches from the console, the following sequence of console
commands can be used: (refer to the console section for more information
on these commands.)
| >>> D/I <WCSA><DATA> ; data <21:8> makes up the control store
; address as shown above.
>>> E/I <WCSD> ; CS data bits <8:0>,<39>,<17:38> are read as
; shown above.
| >>> E/I <WCSA> ; CS data bits <16:9> are read as shown above.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 7
MICROCODE PATCHES 24 Jan 86
2.3 LOADING PATCHES
Patches can be loaded by software through VAX MFPR/MTPR instructions by
using another privileged processor register (WCSL). It is used as a
pointer to a block of patches, which are sequentially loaded by microcode
following an MTPR to this WCSL register.
Seven bytes are required to define each individual patch, with 2 bytes
used for the ROM address being patched and 5 bytes used for the new
controlstore word. When loading patches, all the 7 byte patches, along
with a starting and ending header, are put into a block format as
follows:
Patch block format:
address
55 48 47 40 39 32 31 24 23 16 15 8 7 0
.------+-------+-------+-------+-------+-------+-------.
| # OF PATCHES |CAM ADR| checksum of patches | SRC
+------+-------+-------+-------+-------+-------+-------+
patch 1 |C|0| ROM addrs| 40 bit microword patch | SRC + 7
| | | | <0:13> | <16:9> <8:0, 39, 17:38> |
+------+-------+-------+-------+-------+-------+-------+
patch 2 |C|0| ROM addrs| 40 bit microword patch | SRC + 14
+------+-------+-------+-------+-------+-------+-------+
patch 3 |C|0| ROM addrs| 40 bit microword patch | SRC + 21
+------+-------+-------+-------+-------+-------+-------+
..............................................
+------+-------+-------+-------+-------+-------+-------+
ptch N-1|C|0| ROM addrs| 40 bit microword patch |
+------+-------+-------+-------+-------+-------+-------+
patch N |C|0| ROM addrs| 40 bit microword patch | SRC+(7*N)
+------+-------+-------+-------+-------+-------+-------+
| zero padded to longword boundary |
`------+-------+-------+-------+-------+-------+-------'
2.3.1 FIELD DEFINITIONS OF PATCH BLOCK -
# OF PATCHES:
Unsigned number of seven-byte patches that are to be loaded.
Numbers in the range 0 to 1020 are valid. Numbers not in this
range will produce unpredictable results.
ROM ADDRESS:
Contains the ROM address that is being patched. Bits <9:0> of the
ROM address determine the RAM address into which the 40-bit
microword patch will be loaded.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 8
MICROCODE PATCHES 24 Jan 86
CAM ADDR:
The CAM location to start loading ROM addresses of patched
locations. The internal CAM address will be incremented after a
CAM location is loaded. Numbers in the range of 0 to 159 (10) are
valid. Numbers not in this range will produce unpredictable
results.
C:
If C = 1 THEN the CAM will be loaded with a ROM address and the RAM
will be loaded with a patch. ELSE the RAM will be loaded with a
patch only.
2.3.2 CHECK SUM ALGORITHM FOR PATCH DATA: -
A check sum is generated by a 32-bit unsigned add, ignoring overflows,
of the data starting at the check sum longword and ending at the zero
padding data.
IF checksum NEQ 6969 6969 (hex) THEN fail
ELSE pass.
# of longwords in checksum = ((# patches + 1) * 7 +3) MOD 4
2.3.3 MTPR TO WCSL REGISTER - The WCSL register is written with the
pointer (src) to the block of patches by an MTPR instruction:
WCSL IPR #2E
31 0
+------------------------------------------------------------------+
| physical address of the block of patches |
+------------------------------------------------------------------+
The format for this instruction is:
MTPR src.rl,WCSL
Description:
The MTPR to the WCSL instruction causes the microcode to load the whole
block of microcode patches. The SRC operand contains the physical
address of the block of patches in memory as was shown above. A
| checksum of the block of patches is done by the microcode before
| loading them. If the checksum fails, the patches will not be loaded,
| and the PSL V bit is set as shown below. Otherwise all of the patches
| will be loaded and the PSL condition codes will be set according to the
| SRC operand.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 9
MICROCODE PATCHES 24 Jan 86
| After loading each RAM location, the microcode reads the result to
| assure that it was loaded properly. If not the Vbit is set.
Condition codes:
N <-- src LSS 0 ! if patches are loaded
Z <-- src EQL 0
V <-- 0
C <-- C
N <-- src lss 0 ! if Checksum fails and patches
Z <-- src EQL 0 ! are not loaded.
V <-- 1
C <-- C
2.3.4 INSTALLATION VIA CONSOLE - Although patches are normally
installed with the EEPROM/BI Configurator utility that was written by
Dick Vignoni, they can also be installed from the console. This is
done by by first using the X command to load them into physical memory
and then the D/I command to load them through the WCSL register as
follows: (refer to the console section for more information on the X
and D commands.)
| >>> X <ADDR><COUNT><CR> ; where ADDR is the pointer to the
; patch block and count is the number
; of bytes of data.
>>> D/I <WCSL><ADDR>
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 10
SELFTEST 24 Jan 86
3.0 SELFTEST
3.1 SELFTEST DISCRIPTION
The KA820 CPU module performs module selftest in accordance with the
Scorpio System RAMP spec and the BI Self Test Spec. The microcoded
selftest assures a minimum level of module functionality and provides a
test status through the Status LED's, the Hardware Fault State Bit
(HFSB), and Serial Line Unit 0 (SLU0). Upon successful completion, the
selftest passes microcode control to the system initialization and
booting routines.
The hardware gives microcode control to the selftest routine at the
deassertion of BCI DCLO L. BCI DCLO L assertion to start the selftest
may be caused by a real power-up sequence, by the console test ("T")
command, by software writing the BI RESET bit in the PCntl CSR, or the
SST bit in the KA820's BIIC.
BCI DCLO L deassertion clears the Self Test Pass bit in the PCntl CSR.
When cleared, this bit drives an open collector output to BI BAD L. When
set, this bit drives the two yellow Status LED's. At the conclusion of a
successful selftest, this bit is cleared by microcode, which releases BI
Bad L and lights the two yellow LED's.
From a system's perspective, BI Bad L is a wire-or of the self test
results of all the BI devices in the system. It is used to provide a
visual indication to the front panel of any BI devices that fail their
selftests. Additionally, a bit in the BIIC CSR, called the BROKE bit, is
set by BCI DCLO L and it is cleared by microcode upon successful
completion of the selftest. This bit is used to provide a systemwide
software indication of each BI node's selftest result.
The Hardware Fault State Bit (HFSB) in the CPU's I/Echip is set by BCI
DCLO L deassertion, MIB parity microtraps, and MERR (M Chip error)
microtraps. It is set and cleared under microcode control. The Red
Status LED's on the module are driven to provide a visual display of the
state of the HFSB. The HFSB is cleared prior to selftest to indicate
that patches were loaded successfully and that the first character ( )
was sent to the console.
Selftest outputs ASCII characters to Serial Line Unit 0 (SLU0) only. If
the desired baud rate is not readable from the EEPROM, output is sent at
a default baud rate of 1200 baud. In the multiprocessor environment, the
output to SLU0 is only possible by the primary processor that is attached
to a physical console. Since internode BI traffic is precluded during
the selftest, the BI logical console register is not used for failure
information.
Normally the selftest performs a "slow" comprehensive test which requires
a maximum of 10 seconds to complete. Slow selftest carefully verifies a
kernel of functionality on the module, then expands the level of
verification using only previously tested logic to test new logic
sections. However when BI STF L is asserted, selftest follows a "fast"
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 11
POWERUP SELFTEST 24 Jan 86
path which completes in a maximum of .25 seconds and provides minimal
coverage. Successful execution through either path results in the
release of BI Bad L and passage of microcode control to the
initialization and boot routines.
3.2 SELFTEST USERS AND USES
The KA820 module selftest is applicable to the following areas:
Engineering usage. The selftest routine provides power-up verification
of prototype modules in the Engineering Tester environment.
Manufacturing usage. Selftest may be used as a stimulus in any ATE
testing, environmental testing, or verifiction process which benefits
from the selftest coverage and isolation.
Field Service usage. The selftest is a go/no-go test for the KA820 which
is the lowest level field replaceable unit (FRU) in the system.
Customer usage. The selftest is a go/no-go test. Console output may
provide relevant information to share with the field service office in
the event of a failure.
3.3 SELFTEST PERFORMANCE GOALS
The selftest has the following performance and failsoft goals.
Timing. When BI STF L is not asserted, the KA820 completes self-test
within 10 seconds after the deassertion of BI DCLO L. When BI STF L is
asserted, self-test completes within 250 milliseconds after the
deassertion of BI DCLO L.
Dependency. Selftest has no dependency upon correct operation of other
BI nodes, provided the BI itself is not corrupted by another BI node.
System hardware. Selftest provides maximum coverage for CPU connectors,
sockets, cables, and backplane interconnect in the system.
Power fail. Whenever BCI DCLO L is deasserted, selftest begins.
Unexpected traps. All microtraps that occur during selftest branch to a
special diagnostic trap block. A trap catching register is checked after
each test to detect unexpected traps. Unexpected traps are reported as a
hardware error.
Hardware failure. Selftest attempts to send failure and isolation
information to the console, and then enters console mode.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 12
POWERUP SELFTEST 24 Jan 86
3.4 FUNCTIONAL DESCRIPTION
3.4.1 POWER UP FLOW -
S
L
power up action | HFSB |U| Failure
-------------------------------------------------------+-------+-+---------
1. In hardware; DCLO asserted, DCLO deasserted, | set | |
microcode 0 fetched, Pcntl<Self Test Pass> cleared,| | |
HFSB set, BROKE bit set, red status LED's on. | | |
| | | |
| 2. Set baud rate to 1200; if BI ACLO L is asserted, | | |
| loop here. After 10 sec, print out ?41 to console, | | |
| continue to loop & reprint every 20 min. | | |
| | | |
| 3. Read default baud rate from EEPROM and set UART0 | | | console
| baud rate (default to 1200 if unreadable). | | |
| | |
4. Send <CR><LF>, ASCII "#", turn off HFSB. | clear |#|
| | |
5. Initialize CAM = 7FFF#16, and RAM = | | | console
BROAD.CALL[1DDD#16]. | | |
| | |
6. Load patches, write with read check, | | | console
call[BOOT.LOAD.EEPROM.PATCH]. | | |
| | |
7. Call[BOOT.CHECK.PB.R..E]. If BI STF L is not | | |
asserted or selftest is executing a T command, | | |
go to the slow selftest flow, otherwise go to fast | | |
selftest flow. | | |
| | |
8. Return from selftest. Send ASCII "#", <CR><LF>. | |#|
| | |
9. Go to BOOT.SELFTEST.SUCCESS | | |
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 13
POWERUP SELFTEST 24 Jan 86
3.4.2 SELFTEST FLOW -
|
| SLU0
| output on
| slow selftest action |pass | failing unit(s)
| ---------------------------------+-----+-----------------------------
| 1. Control Store checksum. | A | CS hybrid, CS etch, IE Chip
| 2. IE Chip internals. | B | IE Chip
| 3. DAL Interface | C | IE Chip, DAL etch, M Chip
| 4. M Chip internals. | D | M Chip, Cache, BTB, etch
| 5. BTB array test. (1) | E | BTB, etch
| 6. Cache array test. (2) | F | Cache, etch
| 7. I/E and Mchip interaction | G |
| 8. PCntl internals. | H | PCntl, II, Packet RAM, etch.
| 9. EEPROM checksum. | I | EEPROM, II etch
| 10. Packet RAM test. | J | Packet RAM, II etch
| 11. Fchip test. (3) | K | F Chip, DAL etch
| 12. No NI chipset anymore (4) | . |
| 13. RCX50 test if present. (5) | M | RCX50, cable
| 14. BIIC test | N | BIIC, Pcntl
15. Return to power up flow. | |
fast selftest action |
---------------------------------+-----------------------------------------
1. Enable Cache (2) |
2. Enable F Chip (3) |
3. Return to power up flow. |
| (1) disable bit in EEPROM is checked and BTB enabled, since it must always be
| enabled.
|
| (2) disable bit in EEPROM is checked and cache enabled. This bit is normally
| enabled. Software can disable the cache with the CADR processor register,
| but this doesn't change the state of the EEPROM bit.
|
| (3) disable bit in EEPROM is checked and Fchip enabled prior to selftesting.
| This bit is normally enabled since the Fchip is no longer optional.
|
| (4) disable bit in EEPROM is checked; should always be disabled which disables
| the selftest, since there is longer an NI chipset on the module.
|
| (5) disable bit in EEPROM is checked, and selftest disabled if this option
| isn't present.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 14
POWERUP SELFTEST 24 Jan 86
3.4.3 SELFTEST SECTION DESCRIPTION - Details for each selftest section
are given below.
|
| 1. Checksum control store. Checksum microaddresses 0 to 3FFB with
| patches enabled. This tests all usable ROM locations, CAM, RAM,
| match logic, and the IE Chip control store interface. The result
| is compared to the stored EEPROM constant. If the test fails,
| general purpose registers can be examined in console mode to
| provide the following information:
|
| G[0] = 01000001#16 CONTROL STORE READ CONSTANT TEST; failed when reading
| the EEPROM.
|
| G[0] = 01000002#16 CONTROL STORE CHECKSUM TEST; the checksum was wrong,
| indicating a defective hybrid.
|
| 2. IE Chip internals. Test the internal logic of the IE Chip first.
| The USEQ, EBOX, utraps, and some branch conditions are tested. Any
| failure indicates that the I/Echip is probably defective. If the
| test fails, general purpose registers can be examined in console
| mode to provide the following failure information:
|
| G[0] = 02000001#16 MICROSEQUENCER DATAPATH TEST
| G[0] = 02000002#16 MICROSEQUENCER STACK TEST
| G[0] = 02000003#16 MICROSEQUENCER BRANCH TEST
| G[0] = 02000004#16 MICROSEQUENCER TRAP TEST
| G[0] = 02000005#16 EBOX GPR REGISTER TEST
| G[0] = 02000006#16 EBOX TEMPORARY REGISTER TEST
| G[0] = 02000007#16 EBOX WORKING REGISTER TEST
| G[0] = 02000008#16 EBOX ALU TEST
| G[0] = 02000009#16 EBOX CONDITION CODE TEST
| G[0] = 0200000A#16 EBOX SHIFTER TEST
| G[0] = 0200000B#16 EBOX CONSTANT MUX TEST
| G[0] = 0200000C#16 EBOX SHIFT COUNTER TEST
| G[0] = 0200000D#16 EBOX PROGRAM COUNTER TEST
| G[0] = 0200000E#16 EBOX STATE REGISTER TEST
| G[0] = 0200000F#16 MINT MICROTRAP TEST
| G[0] = 02000010#16 MINT BRANCH TEST
| G[0] = 02000011#16 MINT STATUS REGISTER TEST
| G[0] = 02000012#16 IBOX ACCESS TYPE/DATA LENGTH TEST
| G[0] = 02000013#16 IBOX REGISTER NUMBER TEST
| G[0] = 02000014#16 IBOX BRANCH TEST
| G[0] = 02000015#16 IBOX RLOG TEST
|
| 3. DAL Interface - tests the remaining IE Chip logic that requires the
| DAL; the Memory Interface, IBOX and other branch conditions. Test
| the DAL with MXPR's. Test the M Chip using force cache hit, simple
| MREQ functions. If the test fails, general purpose registers can
| be examined in console mode to provide the following failure
| information about the DAL interface bus:
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 15
POWERUP SELFTEST 24 Jan 86
|
| G[0] = 03000001#16 DAL STUCK-AT TEST (BTB DISABLED)
| G[0] = 03000002#16 DAL STUCK-AT TEST
|
| G[1] = MCHIP STUCK AT ONE, any bits = 1 are stuck at 1
| G[2] = MCHIP STUCK AT ZERO, any bits = 0 are stuck at 0
| G[3] = BTB STUCK AT ONE, any bits = 1 are stuck at 1
| G[4] = BTB STUCK AT ZERO, any bits = 0 are stuck at 0
|
| G[0] = 03000003#16 DAL SHORTS TEST (BTB DISABLED)
| G[0] = 03000004#16 DAL SHORTS TEST
|
| G[1] = MCHIP SHORTED ONE; any bits = 1 were shorted high together
| G[2] = MCHIP SHORTED ZERO; any bits = 0 were shorted low together
| G[3] = BTB SHORTED ONE; any bits = 1 were shorted high together
| G[4] = BTB SHORTED ZERO; any bits = 0 were shorted low together
|
|
| 4. M Chip internals - Finish testing the M Chip. Check all MREQ
| functions, all MXPR's, interrupts, UARTS, and the tag and valid
| arrays for the BTB and Cache. If the test fails, general purpose
| registers can be examined in console mode to provide the following
| failure information about the Mchip:
|
| G[0] = 04000001#16 MTEMP REGISTER TEST
| G[0] = 04000002#16 BTB/CACHE TAG ARRAY TEST
| G[0] = 04000003#16 REFRESH REGISTER TEST
| G[0] = 04000004#16 ADDRESS TRANSLATION LOGIC TEST
| G[0] = 04000005#16 REI LOGIC TEST
| G[0] = 04000006#16 UART LOOPBACK TEST
| G[0] = 04000007#16 INTERVAL TIMER TEST
| G[0] = 04000008#16 TIME OF DAY COUNTER TEST
| G[0] = 04000009#16 BTB INVALIDATE TEST
| G[0] = 0400000A#16 CACHE INVALIDATE TEST
|
|
| 5. BTB test. The BTB is tested with a unique data pattern to each
| location through the array, and then repeated with complimentary
| data. If the test fails, general purpose registers can be examined
| in console mode to provide the following failure information:
|
| G[0] = 05000001#16 BTB ARRAY WRITE/READ TEST
|
| G[1] = Failed bits, which can be used to show the defective as follows:
|
| Bits Device
| ----------- ------
| <31:24> E10
| <23:16> E11
| <15:08> E12
| <07:00> E13
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 16
POWERUP SELFTEST 24 Jan 86
| 6. Cache test - The cache is tested with a unique data pattern to each
| location through the array, and then repeated with complimentary
| data. The cache is then enabled if the test is successful. If the
| test fails, general purpose registers can be examined in console
| mode to provide the following failure information:
|
| G[0] = 06000001#16 CACHE ARRAY WRITE/READ TEST
|
| G[1] = Failed bits, which can be used to show the defective as follows:
|
| Failed bits Device
| ----------- ------
| <31:24> E6
| <23:16> E7
| <15:08> E8
| <07:00> E9
|
| 7. IE and M Chip Interaction Section - These tests are to assure that
| the I/Echip and the Mchip can successfully operate together. If
| the test fails, general purpose registers can be examined in
| console mode to provide the following failure information:
|
| G[0] = 07000001#16 INTERRUPT DISABLE TEST
| G[0] = 07000002#16 MINT PHYSICAL REFERENCE TEST
| G[0] = 07000003#16 IBOX PREFETCH QUEUE TEST
| G[0] = 07000004#16 MINT MINI TRANSLATION BUFFER HIT TEST
| G[0] = 07000005#16 MINT MINI TRANSLATION BUFFER MISS TEST
| G[0] = 07000006#16 MINT FUNCTION TEST
| G[0] = 07000007#16 MINT MISCELLANEOUS BIT TEST
| G[0] = 07000008#16 MINT MICROTRAP TEST
| G[0] = 07000009#16 IBOX DECODE TEST
| G[0] = 0700000A#16 IBOX MICROTRAP TEST
| G[0] = 0700000B#16 EBOX CONDITION CODE TEST
| G[0] = 0700000C#16 EBOX PROGRAM COUNTER TEST
| G[0] = 0700000D#16 ADDRESS TRANSLATION LOGIC STATUS TEST
| G[0] = 0700000E#16 BTB/CACHE TAG HIT LOGIC TEST
| G[0] = 0700000F#16 INTERRUPT REQUEST TEST
|
|
| 8. PCntl test - Tests the Pcntl CSR by moving patterns through the
| data path. If the test fails, general purpose registers can be
| examined in console mode to provide the following failure
| information:
|
| G[0] = 08000001#16 PCNTL CSR WRITE/READ TEST
|
|
| 9. EEPROM test - Checksum the patch and boot portion of the EEPROM.
| The options portion is not checksummed since it is system
| configuration dependent. If the test fails, general purpose
| registers can be examined in console mode to provide the following
| failure information:
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 17
POWERUP SELFTEST 24 Jan 86
|
| G[0] = 09000001#16 EEPROM READ CONSTANT TEST
|
| G[0] = 09000002#16 EEPROM CHECKSUM TEST
|
|
|
| NOTE
|
| The second EEPROM was added to the module after the
| selftest was written, and it therefore is not tested by the
| selftest.
|
|
|
| 10. Packet RAM test. The packet RAMs are tested with a unique data
| pattern to each location through the array, and then repeated with
| complimentary data. If the test fails, general purpose registers
| can be examined in console mode to provide the following
| information:
|
| G[0] = 0A000001#16 PRAM ARRAY WRITE/READ TEST
|
| G[1] = Failed bits; these bits can be translated to a defective RAM as
| follows:
| Failed Bits Device
| ----------- ------
| <31:28,15:12> E39
| <27:24,11:08> E40
| <23:20,07:04> E41
| <19:16,03:00> E42
|
| 11. Fchip test - this test performs a simple functional test on the
| Fchip. Four ADDF instructions are performed with data structured
| to check all the internal DALs and condition codes. The Fchip test
| is enabled by bit <0> of EEPROM location 2009 817E, and it is left
| enabled whether or not the test fails. If the test fails, general
| purpose register R0 contains the following:
|
| G[0] = 0B000001#16 F CHIP INTERFACE TEST
|
| 12. LANCE Chip test - no longer performed bacause there is no longer an
| NI chipset in the module. The selftest looks at bit <3> of EEPROM
| location 2009 8176, which must be = 1 to disable the non-existent
| LANCE chip.
|
| 13. RCX50 test - this test accesses the RCX50 CSRs, as long as the RX50
| is enabled (bit <4> of EEPROM location 2009 8176 must be = 1). If
| the test fails, general purpose registers can be examined in
| console mode to provide the following information:
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 18
POWERUP SELFTEST 24 Jan 86
|
| G[0] = 0D000001#16 RX50 INTERNAL TEST
|
| G[0] = 0D000002#16 RX50 ID TEST
|
|
| 14. BIIC test - tests the results of the BIIC's internal powerup
| selftest, and also performs a series of loopback transactions to
| write to and read from the BIIC's general purpose registers. If
| the test fails, general purpose registers can be examined in
| console mode to provide the following information:
| G[0] = 0E000001#16 BIIC GPR WRITE/READ TEST
|
| G[0] = 0E000002#16 BIIC INTERNAL SELFTEST
|
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 19
POWERUP SELFTEST 24 Jan 86
3.5 POWERUP AND SELFTEST FLOW DIAGRAM
SELFTEST FLOW DIAGRAM
.-----------------------.
| | | DCLO asserted by powerup,
| +---------------->| DCLO deasserted | console T command, SW
| | | HFSB set, red LEDs on | write to PCntl Reset bit,
| | | yellow LEDs off | SW write to BIIC Reset
| `-----------+-----------'
| +---------------->|
| | V
| | .-----------+-----------.
| +-----| AC LO deasserted ? |
| N `-----------+-----------'
| |Y
| V
| .-----------+-----------.
| errors | Set defaults |
| +<----------+ Read EEPROM constants |
| +<----------+ Checksum EEPROM |
| | | Init CAM and RAM. |
| +<----------+ Load patches, write |
| | | read check, enable |
| | | patches. |
| +<----------+ Baud rate range check?|
| +<----------+ Loop back SLU0 |
| | | Turn HFSB off |
| | | Send <CR><LF> |
| | | Send ASCII "#" |
| | `-----------+-----------'
| | |
| | V
| | .-----------+-----------.
| | +----+ T command self test ? |
| | | Y `-----------+-----------'
| | | |N
| | | V
| | V .-----------+-----------.
| | +----+ Fast self test ? |
| | | N `-----------+-----------'
| | | | |Y
| | | | V
| | | | .-----------+-----------. .----------------.
| | | | | Check Fchip and cache +--->| Enable/Disable |
| | | | | enable bits in EEPROM | | Fchip & cache +---->.
| | | | `-----------------------' `----------------' |
| | | | |
| | | | |
| | | |
| | +----------------+ |
| | | |
| | V |
| | .-----------+-----------. |
| +<----------+ Checksum control store| |
| | | Print ASCII "A" | |
| +<----------+ IE Chip internals | |
| | | Print ASCII "B" | |
| +<----------+ DAL INTerface | |
| | | Print ASCII "C" | |
| +<----------+ M Chip internals | |
| | | Print ASCII "D" | |
| | +<----------+ Test the BTB array * | |
| | | | Print ASCII "E" | |
| | +<----------+ Test cache array * | |
| | | | Print ASCII "F" | |
| | +<----------+ Test the I/E, Mchip | |
| | | | interactions | |
| | | | Print ASCII "G" | |
| | +<----------+ Test PCntl CSR | |
| | | | Print ASCII "H" | |
| | +<----------+ Chcksum part of EEPROM| |
| | | | Print ASCII "I" | |
| | +<----------+ Test packet RAM | |
| | | | Print ASCII "J" | |
| | +<----------+ Test Fchip * | |
| | | | Print ASCII "K" | |
| | +<----------+ No LANCE (disabled)* | |
| | | | Print ASCII "." | |
| | +<----------+ Test RX50 * | |
| | | | Print ASCII "M" | |
| | +<----------+ Test BIIC | |
| | | | Print ASCII "N" | |
| | `-----------+-----------' |
| | |<--------------------------------------+
| | V
| | .-----------+-----------.
| | | Send ASCII "#" |
| | | Send <CR><LF> |
| | `-----------+-----------'
| | |
| | V
| | | .-----------------------.
| | | | Do Init Routine |
| | | `-----------+-----------'
| | | |
| | V
| | .-----------------------.
| | | Clear broke bit |
| | | Set selftest pass |
| | |Yellow LED's on,Red off|
| | `-----------------------'
| |
| |
| | .-----------------------.
| +---------->| Console routine |
| | |
+-----------------+ Test command causes |
| DC LO assertion |
`-----------------------'
* These disable bits are first checked in the EEPROM to determine
whether or not to test the function, and in some cases to
enable the function as described in the selftest flow in 3.4.2.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 20
INITIALIZATION 24 Jan 86
4.0 INITIALIZATION
4.1 POWER UP INITIALIZATION
Power-up initialization is only done when power is restored to the system
(DCLO deasserted). This power-up could have been caused by a true power
fail, a console "T" command, by software setting the BI Reset bit in the
PCntl CSR (bit <28> of I/O location 2008 8000), or by an NI reboot which
sets the same bit. Portcontroller and BIIC initialization must be done
BEFORE deasserting BI BAD L (BI self test status signal).
Power-up initialization includes the following:
IEchip
1) Load power-up halt code "03"
Mchip
1) stop time of year clock and clear it.
2) MTEMP15 clear WARM/COLD flags
Portcontroller
1) RXCD .... clear the busy bit
Module BIIC (see BIIC chip specification)
1) Load patch revision number from EEPROM to
the BI device type register.
| 2) Load the BCI control register with 0000 0770 as follows:
31 24 23 16 15 08 07 00
| +---------------+-----------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-----+
| | 0's 0's |0|0|0|0|0|0|0|1|1|1|0|1|1|1|0| 0's |
| +---------------+-----------+|+|+|+|+|+|+|+|+|+|+|+|+|+|+|+-----+
| | | | | | | | | | | | | | |
BURSTEN ------+ | | | | | | | | | | | | | |
IPINTR FORCE ---+ | | | | | | | | | | | | |
MSEN -------------+ | | | | | | | | | | | |
BDCSTEN ------------+ | | | | | | | | | | |
STOPEN ---------------+ | | | | | | | | | |
RESEN ------------------+ | | | | | | | | |
IDENTEN ------------------+ | | | | | | | |
INVALEN --------------------+ | | | | | | |
WINVALEN ---------------------+ | | | | | |
UCSREN -------------------------+ | | | | |
BICSREN --------------------------+ | | | |
INTREN -----------------------------+ | | |
IPINTREN -----------------------------+ | |
PNXTEN ---------------------------------+ |
RTOEVEN ----------------------------------+
3) Clear broke bit if Self-test passed.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 21
INITIALIZATION 24 Jan 86
4.2 PROCESSOR INITIALIZATION
Processor initialization is done during power-up, from the console "I"
command, and before attempting warm or cold boot. Processor
initialization puts the KA820 module into a state such that VAX macro
instructions can be executed. Parts of the initialization are defined in
the VAX SRM (rev 7 page 11-6), and the rest is processor dependent. The
following sections describe what is initialized in each part of the
module.
4.2.1 I/E CHIP INITIALIZATION -
1) Turn off test mode features
2) stop V-bus data reducing
3) Clear VAX trap request bit.
4) Clear re-execute bit.
5) Load new PSL ---- 041F 0000 (16)
6) clear MAPEN bit.
7) Enable memory management traps
8) clear Mini-TB
9) clear hardware fault state bit
10) clear state4 .... currently unused state bit
11) set state5 .... make sure console executing bit
is on. This bit must be clear
BEFORE going to VAX program mode.
12) clear state6 .... exception bit used by interrupts
and exceptions code.
13) clear state7 .... machine check bit used by interrupts
and exceptions code.
14) Halt prefetching.
|
| 15) Clear Istream MTB Load .... turns off Istream MTB load on
| PTE read; loads Dstream only.
|
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 22
INITIALIZATION 24 Jan 86
4.2.2 M CHIP INITIALIZATION -
1) REFR <-- 1 .... Make sure mchip refresh is going
2) P0LR <-- 0400 0000 (16) .... Set ASTLVL to 4.
3) Load new PSL ---- 041F 0000 (16)
4) ICCS .... turn off interval timer
Disable interval timer interrupts
clear interval timer error bit
disable watch dog timer interrupts
5) WDR .... Clear Watchdog timer register.
6) SISR <-- 0 .... Clear software interrupts
7) UART0-3 .... Clear recieve interrupt enable bit
Clear transmit interrupt enable bit
8) ISTATUS .... Clear pending level 14(hex) interrupts.
9) P1LR <-- 0 .... Clear the PME bit.
10) MTEMP15 .... Clear FPD restart code
load logical console byte from EEPROM
11) MTEMP16 <-- 0 .... Clear machine check code.
12) clear BTB .... Clear tags.
13) clear cache .... Clear tags.
4.2.3 F CHIP INITIALIZATION -
1) Nothing.
4.2.4 PORTCONTROLLER INITIALIZATION -
1) CSR .... unlock BI event code
clear IP interrupt bit
disable CRD enable bit
clear CRD interrupt bit
clear RUN light
clear console interrupt bit
disable remote console interrupt
clear write wrong parity bits.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 23
INITIALIZATION 24 Jan 86
4.2.5 BIIC INITIALIZATION -
1) Load BCI register with same contents as
power-up initialization above.
| 2) Load BI device type register from EEPROM.
| (4 consecutive bytes starting at location 2009 8168)
4.2.6 PACKET BUFFER INITIALIZATION -
1) Copy Options and Boot section of EEPROM to packet buffer
starting at location 0.
4.2.7 RX50 INITIALIZATION -
1) Nothing.
4.2.8 WATCH CHIP INITIALIZATION -
1) Nothing.
4.3 SYSTEM BUS INITIALIZATION
| System bus initialization consists of checking each node's broke bit, and
| then loading BI memory nodes' starting and ending addresses. This is
| done at power-up, NI reboot, "T" console command, "B" console command and
| "T /M" console command.
|
| If a node's 'broke' bit is set, it is assumed that the node has not
| completed it's selftest. The CPU then enters a programmable timeout
| loop, based upon an EEPROM stored constant. This wait period that is
| stored in the EEPROM is determined by subtracting the total time for the
| CPU selftest from 10 seconds.
|
| After the timeout period has expired, the microcode then reprobes that
| node and then continues to the other BI nodes. If the CPU now finds a
| 'broke' bit set, it checks to see if it is a memory node. A BI memory is
| defined to have a device type with bits 14-8 equal to zero. The size of
| the BI memory is gotten from the memory CSR located at 100 (hex) offset
| from its BI node space.
|
| If not found to be a memory node, it assumes that it is broken. If it is
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 24
INITIALIZATION 24 Jan 86
| a memory node, it checks bit <12> of the memory CSR register to determine
| if it is broke. If not broke, the BI memory starting and ending
| addresses are then loaded.
|
| For fast selftest the same timeout stored in the EEPROM is used, but now
| the constant should be set to 0, since all nodes should be done their
| fast selftests within 250 ms.
|
| The system bus initialization routine prints to the console the status of
| each node. A "." is printed for a non-existing node, the node number is
printed for a good node, and a "-" is printed in front of the node number
of a broken BI node. Finally the maximum BI memory address is printed in
HEX.
EXAMPLE:
0 1 2 . . -5 . . . . . B . . . .
04000000
Note: node 5 is broke
nodes 0, 1, 2, and B are good.
nodes 3,4,6,7,8,9,A,C,D,E,F do not exist.
0400 0000 (16) is the maximum BI memory address.
4.3.1 BI MEMORY REGISTERS - These two memory registers are accessed by
the initialization microcode.
4.3.1.1 BI MEMORY CSR REGISTER - This register is read at each BI
Memory node to determine the memory size and to check its BROKE bit,
to determine if it passed its own self test.
Address is bb+100. (bb is the BI node space base address)
31 30 29 28 18 17 16 15 14 13 12 11 10 09 08 07 06 00
+--+--+--+------------------+--+--+--+--+--+--+--+--+--+-----+----------+
| | | | MEM SIZE | | | | | | | | | | | |
+--+--+--+------------------+--+--+--+--+--+--+--+--+--+-----+----------+
^
|
BROKE BIT---+
All BI nodes with BIIC device type register bits <14:8> equal to
zero, MUST have a CSR at address bb+100 like the one above. The "MEM
SIZE" field is the memory size in 256 Kbyte increments. If the
memory size field is non-zero, BIIC start/end address registers will
be loaded. The "BROKE BIT" in the memory CSR will indicate if the
module is good or not. The BIIC broke bit will be ignored.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 25
INITIALIZATION 24 Jan 86
4.3.1.2 MEMORY BCI CONTROL REGISTER - This register is located
within the memory module's BIIC. Since the BI memory can't write to
its own BCI CSR, this register must be written with 0000 2100, which
sets the STOPEN and USCREN bits. This enables the BI STOP command
and also enables its User CSR space.
Start
.-----------------+--------------------.
| Start at BI node 0. |
| Load time-out constant from EEPROM |
`-----------------+--------------------'
| .------------------------------------------>|<------------------------------.
| | V |
| | .-----------------------------. |
| | | Read BIIC status register | | .---------------------.
| | `---------------+-------------' | | |
| | V | Y V |
| | .----------------. Y .-----+-------------. N .--------+----------.
| | | Broke bit set? +--------------->| time-out reg = 0? +------>| decrement timeout |
| | `-------+--------' `-------------------' `-------------------'
| | | N
| | V
| | .--------------------------------------.
| | | Read BI node device type register |
| | Device type of `--------+--------+-------+-------+----' Non-existing BI node. .----------------------.
| | 0000 or FFFF hex. | | | `----------------------------->| Print "." to console.|
| | .-------------------------' | | `----------+-----------'
| | | | | |
| | | BI memory node. | | BI device node. |
| | | .------------' `---------------. |
| | | V V |
| | | .---------------------------------. | |
| | | | Initialize BIIC. | | |
| | | | Read memory CSR for SIZE and | | |
| | | | BROKE bit. | | |
| | | | Load BIIC Start/End address | | |
| | | | register for memory nodes. | | |
| | | `--------------+------------------' | |
| | | `----------. .--------------------' |
| | | V V |
| | | .----------. No |
| | | | Broken? |-------------------------------------------------->|
| | | `-----+----' |
| | `---------------------------------> | Yes |
| | V |
| .-----------------------. |
| | Print "-" on console. | |
| `-----------+-----------' |
| V |
| .-----------------------+----------------------. |
| | Print BI node number and space on console. | |
| | Update maximum memory register. |<--------------------------------'
| | Increment BI node number. |
| `-----------------------------+----------------'
| V .-------------------------------.
| No .--------+---------. Y | Print <CR><LF> to console. |
`<---------------------------------------| BI node = 16? +--------------->| Print Maximum memory address. |
`------------------' | Print <CR><LF> to console. |
`----------------+--------------'
V
DONE
figure 4.1 FLOW FOR LOADING STARTING AND ENDING ADDRESSES TO BI MEMORY
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 27
INITIALIZATION 24 Jan 86
4.3.2 BI NODE REGISTERS USED -
4.3.2.1 BIIC DEVICE TYPE REGISTER - This register is read at each BI
node to determine which nodes are present and which are memory nodes.
(see BI specification for more details):
Address is bb+00. (bb is the BI node space base address)
31 16 15 0
+-------------------------------+-------------------------------+
| Rev code | Device type |
+-------------------------------+-------------------------------+
If bits <14:8> equal zero then device is a BI memory.
If bits <15:0> equal FFFF (hex) or 00000 then device is still
initializing or broke.
4.3.2.2 BI CONTROL AND STATUS REGISTER - This register must be read
at all non-memory nodes to determine if each device passed its self
test. On memory nodes, the BROKE bit is located within the Memory
CSR register, since the memory can't write to its own BI CSR
register.
Address is bb+04. (bb is the BI node space base address)
31 24 23 16 15 10 08 07 03 00
+---------------+---------------+-+-+-+-+-+-+-+-+-+-+---+-------+
| 0's | BIIC Type | | | | | | |0| | | |ARB|Node ID|
+---------------+---------------+|+|+|+|+|+|+-+|+|+|+---+-------+
| | | | | | | | |
HES ---+ | | | | | | | |
SES -----+ | | | | | | |
INIT ------+ | | | | | |
* BROKE -------+ | | | | |
STS -----------+ | | | |
SST -------------+ | | |
UWP -----------------+ | |
HEIE ------------------+ |
SEIE --------------------+
* Broke bit for BI device nodes. Cleared by
BI node if its self-test passed.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 28
BOOTING 24 Jan 86
5.0 BOOTING
5.1 BOOT MICROCODE
This code is entered from power-up, from a VAX HALT instruction, and from
a machine error halt. If PCntl CSR bit <31>, RSTRT/HALT, is set to a
'1', which is the HALT position, control is passed to console microcode,
otherwise a reboot is attempted. Microcode has internal flags that
signal whether a WARM or COLD boot is in progress. This is to insure
that the machine does not loop forever on trying to reboot. The WARM
boot flag is in the Mchip register MTEMP15 bit 27 and the cold boot flag
is bit 26.
5.1.1 WARM BOOT - Steps to a warm boot are the following:
1. Check internal WARM and COLD boot flags. If either the WARM or
COLD flags are set, then WARM boot fails and a COLD boot is
attempted.
2. Set the WARM boot flag.
3. Find a valid Restart Parameter Block (RPB). If none is found, the
WARM boot fails. (see next section for RPB search algorithm).
4. Check the software restart in progress flag in the RPB. If set,
the restart fails.
5. Load the SP with address RBP+512.
6. Load the Argument Pointer (AP) with halt code describing reason for
REBOOT.
7. Do processor initialization.
8. Turn on the front panel RUN light.
9. Start processor at the restart address (longword at address RPB+4).
5.1.1.1 FIND RPB ALGORITHM - Finding a Restart Parameter Block (RPB)
is done as part of a WARM restart. The algorithm is as follows:
Restart Parameter block
RPB + 00 physical address of the RPB. (must be page aligned.)
RPB + 04 physical address of the restart routine (cannot be 0)
RPB + 08 checksum of the 1st 31 longwords of restart routine
RPB + 0C software restart in progress flag, bit 0.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 29
BOOTING 24 Jan 86
1. Starting at physical address of 0000 0000, search for a page of
memory that contains its own address in the first longword through
the end of memory. If no such page is found, then the Restart
Parameter search fails. The maximum physical address is found when
loading the BI memory starting and ending address.
2. If second longword of page is zero, or not a valid address, then
return to step 1 and continue searching. The second longword
contains the address of the restart routine.
3. Calculate the 32-bit unsigned sum of the first 31 longwords of the
restart routine. If the sum is not equal to the third longword of
the page, then return to step 1 and continue searching.
4. Valid RPB found.
5.1.2 COLD BOOT - Steps to a cold boot are the following:
1. If the cold boot flag is set, then COLD boot fails and control
passes to console microcode.
2. Set the COLD boot flag
3. Find 64K of good memory. If not found then COLD boot fails and
control passes to console mode.
4. Load General Purpose Registers:
R0 not touched
R1 not touched
R2 not touched
R3 In console mode, for a "B ddan<CR>" command, R3 is
loaded with "ddan". For all other cases it is
loaded with zeros to indicate the default boot device.
R4 not touched
R5 In console mode, if B/R5:<data> is specified, R5 is
loaded with <data>. For an NI reboot, R5 is loaded
with a boot parameter (see the NI reboot section).
For all other cases R5 is loaded with zeros.
R6 not touched
R7 not touched
R8 not touched
R9 not touched
R10 HALT PC. (unpredictable on power-up)
R11 Halt PSL. (unpredicable on power-up).
AP Halt code. (see table in CONSOLE section).
FP not touched
SP Address of 512 bytes past start of good memory.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 30
BOOTING 24 Jan 86
5. Turn on the RUN light.
6. Jump to macrocode at physical address 2009 0104 (hex) in the Packet
buffer.
The packet buffer code is responsible for bringing in VMB (in the VMS
| case) off of a disk or the RX50. From there VMB loads SYSBOOT which
| finally brings in VMS. Other operating systems will use different boot
programs, but the flow is basically the same.
5.1.2.1 FIND 64K GOOD MEMORY ALGORITHM - The Find 64K of good memory
is executed by the "B" command, the "T/M" command and also during a
COLD boot. The algorithm for finding 64K of good memory has two
parts. The first part does a quick RAM test to find 64K of good
memory. This consists of a marching 1's test through 64K of BI
memory, and if an error is detected, restarting on the next page and
continuing until 64K is found that is error free. If 64K of good
memory is found, the following additional testing is done. This
second part checks pieces of the BI memory board that are untested by
its own module self-test.
The main logic missed by the internal self test is the BIIC to Gate
Array interconnect and the command decode logic. ECC logic is also
missed but the scope of the extended memory tests can't easily test
this. Listed below are the tests done in the extended memory test to
the BI node on which 64K of good memory is found. If 64K isn't
found, or if this second part of the testing fails, the COLD boot
fails and control is passed to the console microcode.
5.1.3 VAX INSTRUCTIONS TO CLEAR WARM/COLD FLAGS - Once the operating
system is restarted or booted, it must clear the WARM and COLD boot
flags before another AUTO-REBOOT can take place. This is done by
writing to TXDB (IPR 23 HEX) using an MTPR instruction with the
following data:
0000 0F02 causes reboot using default device.
0000 0F03 clears WARM boot flag.
0000 0F04 clears COLD boot flag.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 31
BOOTING 24 Jan 86
5.1.4 BOOT SUMMARY - Summary of boot code modules executed by console
commands, reboot, and during power-up.
| | | DCLO caused by: TRUE power loss, |
| Console commands | Vax Error Halt | or Portcontroller CSR reset bit. |
Boot section | | | | | | | | or HALT instr. | slow | Fast |
| B | I | T |T/M | S | C | N |warm cold halt | Warm cold Halt | warm cold Halt |
--------------------------|----|---|----|----|----|----|----|---------------------|------------------|------------------|
Load EEPROM patches | - | - | X | - | - | - | - | - - - | X X X | X X X |
--------------------------|----|---|----|----|----|----|----|---------------------|------------------|------------------|
Slow self-test | - | - | X | - | - | - | - | - - - | X X X | - - - |
--------------------------|----|---|----|----|----|----|----|---------------------|------------------|------------------
processor initialization | X | X | X | X | - | - | - | X X ? | X X X | X X X |
--------------------------|----|---|----|----|----|----|----|---------------------|------------------|------------------|
System initialization | X | - | X | X | - | - | - | - - - | X X X | X X X |
--------------------------|----|---|----|----|----|----|----|---------------------|------------------|------------------|
Find RPB | - | - | - | - | - | - | - | X X ? | X X ? | X X ? |
--------------------------|----|---|----|----|----|----|----|---------------------|------------------|------------------|
Find 64K good memory | X | - | - | X | - | - | - | - X ? | - X ? | - X ? |
and extended memory test | | | | | | | | | | |
--------------------------|----|---|----|----|----|----|----|---------------------|------------------|------------------|
Enter VAX program mode | X | - | - | X | X | X | X | X X - | X X - | X X - |
--------------------------+----+---+----+----+----+----+----+---------------------+------------------+------------------'
"X" -- code module executed in normal path.
"-" -- code not executed in path
"?" -- code not executed if HALT/BOOT switch is halt or WARM/COLD flags both set.
code is executed if HALT/BOOT switch is BOOT and WARM/COLD boot fails.
5.1.5 BOOT EXAMPLES - The following sections will show examples of the
different ways a scorpio system can be booted.
5.1.5.1 NORMAL SINGLE PROCESSOR BOOT -
TTY
|
.-----------. | .------------. .-----------.
| KA820 |-' | BI memory | | disk |
| |Boot | | | |
`-----+-----'console: UART0 `-----+------' `-----+-----'
| | |
---------+---------------------------+------------------------+----- BI
For a base system the boot will go as follows. On power-up, the
KA820 will do self-test, power-up initialization, processor
initialization, system initialization and then run boot code from the
packet buffer that was copied from the EEPROM. This code would then
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 32
BOOTING 24 Jan 86
read in the VMB boot code from the RX50 floppy disk or the system
disk.
5.1.5.2 ASYMMETRIC MULTIPROCESSOR SYSTEM (BI BOOT). -
TTY .----------. boot .-----------. halt
`-----| A | console enabled | B | console enabled
| KA820 | console: UART0 | KA820 | console:
`----+-----' `-----+-----' BI node A
| |
---------+----------+------------------+---+------------ BI
| |
.--------+-------. .-----+-----. halt
| Disk | | C | console enabled
`----------------' | KA820 | console:
`-----------' BI node A
In this configuration, A is the primary processor, and B and C are
called attached processors. When power is applied, all three
processors go through their normal powerup sequence. A, B, and C
each do a self-test, followed by power-up, processor, and system
initialization. The three processors all load starting and ending
addresses for BI memory using the same algorithm. B and C then go to
console mode and try to send the '>>>' prompt to processor A.
Processor A then boots the operating system by first using the EEPROM
macro code (copied to the packet buffer) to read in the VMB boot
program off the disk. Once up and running, A then boots B and C
using the special RXCD MTPR and MFPR instructions to send console
commands and receive console responses.
6.0 EEPROM CONTENTS
| The first revision of the KA820 (rev A1) contained a single 8K X 8 EEPROM,
| and subsequent revisions contain two EEPROMs. They are used to store
| changeable data such as option information, VAX macro boot code, and
| control store patches. The modules with a single EEPROM are constrained to
| having a little over 1000 bytes available for boot code. Those modules
| that have two EEPROMs use this space in the first EEPROM for a boot
| dispatcher, and the boot code for each device is in the second EEPROM.
|
| Other than not containing actual bootcode, the primary EEPROM in later
| modules contains essentially the same information as the single EEPROM in
| rev A1 modules.
|
| Physical address bit <0> is not used in addressing the EEPROM, and
| consequently only even addresses are used. i.e. The first byte is
| addressed at location 2009 8000(hex), the second byte at 2009 8002 and so
| on, through 2009 BFFE for the first EEPROM. Those modules that contain 2
| EEPROMs have 8K bytes of additional space from 2009 C000 to 2009 FFFE.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 33
EEPROM CONTENTS 24 Jan 86
| A summary of the EEPROM contents is shown in fig. 6.1, and this is
| followed by a bit level description of the EEPROM contents on the next
| page. Note also that there is a significant amount of information that was
| for the NI which is no longer used.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 34
EEPROM CONTENTS 24 Jan 86
Abbreviations used in the EEPROM Map include:
II: RCX50 ENABLE //: UNUSED
BI: BI logical console node number 00: UNUSED = 0
UA: UART0 BAUD RATE LD SA: LOAD SERVER ADDRESS
OP: OPTIONS (FCHIP, BTB, CACHE) IN RV: EEPROM INIT REV
1E 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 00 <--Address offset of
| | | | | | | | | | | | | | | each byte
+-------------------------------------------------+
| 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 FF | 20098000
+------------+-----------------------------+------+
| | ld sa | module serial number |00 00 | 20098020
| +------------+-----------------------------+------+
| | 14 bytes unused/ all 0s |ld sa | 20098040
| +------------------------------------------+------+
| ~ 48 bytes unused/ all 0s ~ 20098060
| +------------------------+------------------------+
| | 8 bytes Reserved / CSS | 8 bytes unused/ all 0s | 200980C0
| +---------+-----+--------+------------------------+
| |3 unused |in rv|boot inf| 8 bytes unused/ all 0s | 200980E0
+---------+-----+--------+------------------------+
| Boot Message | 20098100
+------------------------+------------------------+
| 8 bytes reserved /users| Boot Message | 20098120
+------------------------+-----------+------------+
| | BI timeout |// AA|// //|// // // //| 00 00 00 00| 20098140
| +------------+--+--+-----+-----+-----+------------+
| |OP UA 00 BI |II|// // //| REV |01 05| // // // //| 20098160
+------------+--+--------+-----+-----+------------+
| Boot B addr|Boot B name|Boot A addr|Boot A name | 20098180
+------------+-----------+-----------+------------+
| Boot D addr|Boot D name|Boot C addr|Boot C name | 200981A0
+------------+-----------+-----------+------------+
| | CHECKSUM CS w/patches | 8 bytes unused/ all 0s | 200981C0
+------+----------------+-------------------------+
| 01 33| 14 bytes reserved for DEC | 200981E0
+------+-----------------------------+------------+
| VAX Boot code | CHECKSUM | 20098200
+------------------------------------+------------+
~ ~
+-------------------------------------------------+
| VAX Boot code | 200984E0
+---------------------------+-----+--+------------+
| Microcode Patches | # |CA| CHECKSUM | 20098A00
+---------------------------+-----+--+------------+
~ ~
+-------------------------------------------------+
| Microcode Patches | 2009BFF0
+-------------------------------------------------+
figure 6.1 EEPROM Summary
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 35
EEPROM CONTENTS 24 Jan 86
*****************************************************************************
* TABULAR SUMMARY OF EEPROM CONTENTS *
*****************************************************************************
2009 8000 FF Constant used in EEPROM test
2009 8002 55 Constant used in EEPROM test
2009 8004 14 BYTES MBZ
| 2009 8020 2 bytes unused (=0)
| 2009 8024 10 Bytes Module Serial number
| 2 chars=plant code (SG, NI or GA)
| 3 char numeric date code YWW Y=year WW=week
| 5 char numeric serial module serial number
|
| 2009 8038 6 byte Load Server Address (For DEBNT - ie. the AIE)
| 2009 8044 70 bytes unused and = 0
| 2009 80D0 8 bytes unused; RESERVED FOR DEC CSS
| 2009 80E0 8 bytes unused (=0)
| 2009 80F0 1 bytes = number of bytes to compare in the boot message
| 2009 80F2 1 byte = location of 1st PARAMETER field in the boot message
| expressed as offset from the start of the receive buffer
| 2009 80F4 1 byte = location of 2nd PARAMETER field in the boot message
| 2009 80F6 2 bytes EEPROM initialization file revision number
| 2009 80FA 3 bytes unused
BOOT MESSAGE
2009 8100 24 bytes = the expected boot message
2009 8130 8 bytes unused; RESERVED FOR USERS
2009 8140 4 bytes unused = 0
| 2009 8148 4 bytes unused
2009 8150 2 bytes unused.
2009 8154 1 byte = AA, the constant that is used in the EEPROM test
2009 8156 1 byte unused
2009 8158 4 bytes for the BI selftest timeout constant
Incremental value = .2 useconds/increment
| 2009 8160 4 byte unused
BI DEVICE TYPE DATA
2009 8168 2 bytes BI device type for module = 0105 (HEX) for KA820
2009 816C 2 bytes BI Rev level for module
bits <15:11> CPU REV
bits <10:1> PATCH REV
bit <0> SECONDARY PATCHES NOT NEEDED default=1
2009 8170 3 bytes unused
2009 8176 1 byte for RCX50 SELFTEST DISABLE.
| Bit <3>: Previously LANCE DISABLE - MUST BE 1 (Disabled)
Bit <4>: RCX50 SEFLTEST DISABLE (0 = enable, 1 = disable)
Bits <7:5,2:0> = 0
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 36
EEPROM CONTENTS 24 Jan 86
CONSOLE SOURCE DATA
2009 8178 1 BYTE
Bits <3:0> BI node number of logical console (default=2)
| 4 bits MBZ
| 2009 817A 1 byte MBZ (previoulsy NI Reboot Enable)
2009 817C 1 byte UART0 baud rate - default=1200 baud
bits <7:0> = Baud rate as follows:
30 --- 150 baud 34 --- 2400 baud
31 --- 300 baud 35 --- 4800 baud
32 --- 600 baud 36 --- 9600 baud
33 --- 1200 baud 37 --- 19200 baud
2009 817E Fchip, BTB, and CACHE disable bits
bit <0> (1 = Fchip disabled; 0 = Fchip enabled)
| bit <1> BTB disable - MBZ (ALWAYS ENABLED)
bit <2> (1 = cache disabled; 0 = cache enabled)default=enabld
| bits <7:3> MBZ
| BOOT DEVICE DATA ****UNUSED AND = 0 ON NEW REV MODULES WITH 2 EEPROMS****
2009 8180 4 bytes --- ASCII code for boot device A /(=0)
2009 8188 4 bytes starting address of device A boot code /(=0)
2009 8190 4 bytes --- ASCII code for boot device B /(=0)
2009 8198 4 bytes starting address of device B boot code /(=0)
2009 81A0 4 bytes --- ASCII code for boot device C /(=0)
2009 81A8 4 bytes starting address of device C boot code /(=0)
2009 81B0 4 bytes --- ASCII code for boot device D /(=0)
2009 81B8 4 bytes starting address of device D boot code /(=0)
| 2009 81C0 8 bytes unused (=0)
2009 81D0 8 bytes: 40 bit checksum of control store with primary
patches installed.
2009 81E0 Unused, RESERVED FOR DEC
2009 81FC 1 byte; constant 33 used in EEPROM test
2009 81FE 1 byte; constant 01 used in EEPROM test
EEPROM BOOTCODE SECTION
2009 8200 4 bytes of checksum for 1020 bytes (DEC)
of bootcode
2009 8208 1020 bytes avail for VAX boot code.
to In new rev module will contain only the boot dispatcher
2009 87FE
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 37
EEPROM CONTENTS 24 Jan 86
EEPROM PATCH SECTION
2009 8A00 4 bytes of checksum for all the patches
2009 8A08 1 byte for the starting CAM address
2009 8A0A 2 bytes showing the number of patches
2009 8A0E Start of patches,
up to 7 bytes per patch....
2009 BFFE up to 984 patches (base 10)
| *************************************************************************
| * LAYOUT OF THE 2ND 8K EEPROM (only on module revs above A1) *
| *************************************************************************
|
| Note:: addressing is the same as for 1st EEPROM with bit 14 being
| set to select the 2nd EEPROM
|
| 2009 C000 Default boot device designation of form DDnu (4 bytes)
| 2009 C008 Default T/M boot device designation of form DDnu (4 bytes)
| 2009 C010 Bootcode descriptor A (8 bytes)
| 2009 C020 Bootcode descriptor B (8 bytes)
| 2009 C030 Bootcode descriptor C (8 bytes)
| 2009 C040 Bootcode descriptor D (8 bytes)
| 2009 C050 Bootcode descriptor E (8 bytes)
| 2009 C060 Bootcode descriptor F (8 bytes)
| 2009 C070 Bootcode descriptor G (8 bytes)
| 2009 C080 Bootcode descriptor H (8 bytes)
| 2009 C090 Bootcode descriptor I (8 bytes)
| 2009 C0A0 Bootcode descriptor J (8 bytes)
| 2009 C0B0 BOOTCODE - including chksum
| : : :
| : : : 8104 bytes (base 10)
| : : :
| 2009 FFF6 BOOTCODE
| 2009 FFF8 67 last 4 bytes used for EBKAX diagnostic
| 2009 FFFA 69 " " " "
| 2009 FFFC 56 " " " "
| 2009 FFFE 52 " " " "
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 38
EEPROM CONTENTS 24 Jan 86
6.1 CHECKSUM ALGORITHM FOR EEPROM DATA
A checksum constant is stored as the first 4 bytes of both the bootcode
section of the EEPROM, and the patch section. The checksum is generated by
a 32-bit unsigned add, ignoring overflows, of the data in the section plus
this data that's stored in the first longword. The first longword is used
to force the result of the checksum to be 6969 6969 hex.
checksum = 6969 6969 hex = (longword checksum)
+ (longword sum of data in section)
The 40 bit checksum that's stored within the EEPROM for the control store
with patches installed is whatever number the checksum comes out to be.
6.2 READING AND WRITING THE EEPROM
The EEPROM is normally loaded by the EEPROM/BI Configurator utility
program. This is used to examine, modify, and update the EEPROM, and is
the way that primary patches get loaded from floppy disk distribution media
in the field.
| NOTE: The console (D)eposit command may be used to change any EEPROM
| location as long as the physical I/O address is used.
A limited number of locations within the EEPROM can also be changed with
the console Deposit command, using the /E qualifier. These locations are
the 24 customer configurable locations which include:
EEPROM TYPED
ADDRESS LOCATION CONFIGURATION USE
(hex)
2009 8170
to
2009 8174 00-02 Reserved for future use.
2009 8176 03 RX50 disable
2009 8178 04 unused
2009 817A 05 unused
2009 817C 06 UART0 baud rate
2009 817E 07 Fchip, BTB, and cache disables
| 2009 8180 08-17 Boot devices and addresses
| to *** Unused on boards above rev A1 (=0) ***
| 2009 81B8
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 39
CONSOLE 24 Jan 86
7.0 CONSOLE
KA820 console functions are implemented in microcode, and the console
supports the VAX Midrange Console subset as specified in Chapter 11,
'VAX-11 Console and System Bootstrapping', of the SRM, Rev 7. The only
command not supported is <RUBOUT>. Console I/O is supported from UART0 and
also from a remote console via the BI. In this section the console
sources, selection of the Console, and the V-11 supported Console commands
and syntax are covered.
7.1 CONSOLE SOURCES
There are two possible console sources. A physical console connected to
| UART0 and a logical console over the BI. A backpanel signal selects
| between a physical and a logical console. PNL CNSL LOG H is held low on
| the primary processor which selects a physical console. This signal is
| high on any attached processors to select a logical console. Console I/O
| of the logical console is to the primary processor BI node, as specified
| by a location within the attached processor's EEPROM.
7.1.1 UART0 - The characteristics of UART0 are
1. No parity.
2. Baud rates 150, 300, 600, 1200, 2400, 4800, 9600, 19200 can be
used. Default baud rate is obtained from the EEPROM.
3. The Baud rate can be changed using <BREAK> while in console I/O
mode, see the description of "CONSOLE AUTOBAUD".
| 7.1.2 BI NODE AS A CONSOLE - The purpose of using a BI node as a
| console source is to control multi-processor Scorpio systems from a
| single physical console. The console Z command, and MFPR/MTPR
| instructions are normally used to communicate via the logical console
| over the BI.
|
| Console communication over the BI is performed using the VAXBI RECEIVE
| CONSOLE DATA REGISTER, called the "RXCD" register. The RXCD register
| is located in BI Node Register address space, and it is addressed by
| microcode at the base address of the node's BI nodespace + 200.
|
| To send a character to BI node N, node N's RXCD register is first
| written with the character. Node N then reads the character from its
| own RXCD register. An unmaskable interrupt is generated within the
| KA820 processor each time a new character is written to its RXCD
| register.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 40
CONSOLE 24 Jan 86
As an example, consider a two-processor system consisting of a Primary
Processor (PP) and an Attached Processor (AP):
------+-----------------------+-------------------- BI
| |
+------------+ +------------+
| | RXCD | | | |RXCD| |
| +------+ | | +----+ |
| KA820 (PP) | | KA820 (AP) | ... (other nodes)
| | | |
| BI node 0 | | BI node 4 |
| +--------+ | Console | | LOGICAL console NODE 0.
| | UART-0 | | Enabled | | Console enabled.
+------------+ +------------+
|
LA120
The operator can start a console command dialogue with the PP by typing
<control>P on the LA120 (if the console is enabled). With the PP in
console mode (halted), the operator can start a console command
dialogue with the AP by typing Z 4<CR> to select the AP, and then
typing <ESC><control>P. Upon receiving the <Control>P, the AP enters
console mode and accepts further console commands. The console
microcode uses the scheme described in the next section, and the Z
command is described in the section on Console Commands.
System software running in the PP can also create a console command
| dialogue with an AP, through a half-duplex path between the RXCD
| registers of the two KA820s:
An MTPR executed on the PP, can be used to a
character to the RXCD register of the AP,
which the AP will interpret as a console
command character. The AP will respond by
sending a console response to the RXCD
register of the PP, which can then be read by
the PP with an MFPR.
The VAX instructions MTPR and MFPR used for this purpose are described
in a later section.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 41
CONSOLE 24 Jan 86
7.1.2.1 CONSOLE COMMUNICATION OVER THE BI - The console microcode
uses the following scheme to communicate over BI.
The characters are written one at a time over the BI to the
destination BI node's RXCD using the format:
RXCD register format:
31 16 15 14 12 11 8 7 0
,----------------------------+--+--------+---------+----------------,
| MBZ |B | MBZ |from node| data |
`----------------------------+--+--------+---------+----------------'
RXCD Bit <15>: 'BUSY' bit.
The receiving node changes this bit from 1 --> 0
when the read is done.
Other BI nodes only change this bit from 0 --> 1
when writing to the RXCD.
Bits <11:8>: sender's BI node #.
Bits <7:0>: console character
To write to the RXCD, a BI node performs a 'READ' to the I/O space
address corresponding to the destination BI node's RXCD and examines
bit <15>.
BIT<15> = 0: Write the word containing the data,
BI node #, and bit <15> = 1;
Bit<15> = 1: Remote node is busy.
The receiving BI node performs a READ - WRITE sequence to its own
'RXCD' register to read the character and to change BIT <15> from 1
to 0.
|
|
| NOTE
|
| Because of hardware restrictions, the microcode does not use
| interlocked read and writes when in console mode or during
| MTPR/MFPR instructions. If macro software uses interlocks
| when accessing the RXCD, it can use modify or interlocked
| instructions with the virtual address of the RXCD. These
| will work fine with other interlocked instructions, but they
| won't lock out console generated commands or MTPR/MFPR
| instructions.
|
|
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 42
CONSOLE 24 Jan 86
7.1.2.2 MFPR, MTPR INSTRUCTIONS FOR RXCD REGISTER -
MFPR #REMOTE_CONSOLE_RECEIVE, dst.wl
Purpose:
Read from the Remote console receive register in
the portcontroller.
Operation:
If PSL<current-mode> NEQ 0, Then {reserved instruction
fault}
dst<--READ [remote console receive register]
If NOT dst <15> then
begin
set PSL <V>; ! no character received
Exit;
end;
Clear PSL<V>; ! character received
WRITE [remote console receive register] <-- 0;
Condition codes:
N <- received longword LSS 0
Z <- received longword EQL 0
V <- SET if character not received
Cleared if character received
C <- C
NOTE: dst.wl contains RXCD <15:0>
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CONSOLE 24 Jan 86
MTPR data, #REMOTE_CONSOLE_TRANSMIT
*Where "data" is:
31 12 11 8 7 0
.--------------------------+----------+-----------.
| MBZ | TO NODE | Char |
`--------------------------+----------+-----------'
Purpose:
Write to an abitrary BI nodes remote console
receive register.
Operation:
If PSL<current-mode> NEQ 0 Then {reserved instruction
fault}
temp1<--READ [remote console receive register of
destination]
If temp1<15> then
begin
set PSL<V>; (failure in writing data)
Exit;
end;
Clear PSL<V>; (success writing data)
WRITE [remote console receive register of destination] <--
31 16 15 12 11 8 7 0
,---------------------+------+---------+----------,
| 0 | 1000 |FROM NODE| char |
`---------------------+------+---------+----------'
Condition codes:
N <- received longword LSS 0
Z <- received longword EQL 0
V <- 1 if character sent / 0 if character not sent.
C <- C
NOTE: If the destination's RXCD is not busy, it is written with
the busy bit set to 1.
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CONSOLE 24 Jan 86
7.2 CONSOLE I/O MODE ENTRY
V-11 console I/O mode can be entered in one of the following ways:
1. FROM PROGRAM I/O MODE
| a). Console is ENABLEd and _^P was received from UART0 of
| the PP's physical console, or from the PP's BI node
| if the it is an AP. A flowchart of this process is
| shown below.
b). A VAX ERROR HALT occurred or a VAX HALT instruction was
executed in kernel mode and the HALT/RESTART switch is
in the HALT position, or the switch is in the RESTART
position and a cold restart failed.
2. POWER-UP: (see POWER-UP BOOT FLOW CHART, Section 1.0)
a). The slow self test failed,
b). The HALT/RESTART switch is in the HALT position or
c). The HALT/RESTART switch is in the RESTART position
and a cold start failed.
The Console I/O mode to Program I/O mode transition occurs in response to
console commands B, C, N, S and T/M. From the N(ext) command, console
I/O mode is re-entered after executing one VAX instruction.
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CONSOLE 24 Jan 86
.--------------------.
| PROGRAM IO MODE |
| 32 LEVEL INTERRUPT |------------------------------------------.
`----------+---------' RXCD INTERRUPT |
| |
UART0 INTERRUPT V V
.------------------. NO .-------------.
| Char = ^P ? |-------->----->|<-----------<------| CHAR = ^P ? |
`--------+---------' | `------+------'
| | |
V YES | V
.------------------------. | SECURE .---------------------------.
| console enable/secure ?|---->---->|<----<------| CONSOLE ENABLE/SECURE ? |
`---------+--------------' V `-------------+-------------'
| | |
V ENABLE | V ENABLE
.-----------------------. LOGICAL | PHYSICAL .------------------------.
| physical/logical ? |----->---->|<----<-------| PHYSICAL/LOGICAL ? |
`---------+-------------' | `------------+-----------'
| PHYSICAL | |
V | |
.------------------. | |
| CONSOLE I/O MODE | | |
| | | |
| | | V
`------------------' | .------------------.
V | CONSOLE I/O MODE |
.-------------------. `------------------'
| REQUEUE INTERRUPT |
| AT BR4 LEVEL |
`-------------------'
Figure 7.1 CONSOLE MODE ENTRY FOR <CTRL> P
7.3 SCORPIO CONSOLE COMMANDS AND SYNTAX
The SCORPIO Console implements the subset commands specified in the
'Vax-11 Console and System Bootstrapping', Chapter 7 of the SRM, Rev 7,
with the exception of the <RUBOUT> command. There are also some
additional commands which facilitate VAX macro instruction single
stepping, and the Z command for forwarding console commands to another BI
Node. A complete list of commands, error messages, and command syntax
are detailed in the following sections.
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CONSOLE 24 Jan 86
7.3.1 SCORPIO MRCS SUPPORTED COMMANDS - The SCORPIO Midrange console
supports the following single letter commands (abbreviated to the first
letter of the command):
NOTE: SCORPIO Console supports only one letter commands;
Command words are not supported.
B - BOOT N - NEXT
C - CONTINUE S - START
D - DEPOSIT T - TEST
E - EXAMINE X - XFER
H - HALT Z - Z (BI FORWARD)
I - INITIALIZE ! - ! (comment)
CONTROL CHARACTERS control-P, control-S, control-Q,
control-U
CR (CARRIAGE RETURN), <ESC>, and <BREAK>.
The Z command and the characters <ESC> and <BREAK> are unique to
the KA820 and are not specified in the VAX SRM.
The commands F (Find) and U (Unjam), and the characters <del>
and <backspace> are not recognized and are echoed as <BEL>.
7.3.2 SCORPIO COMMAND SYNTAX - The syntax of each Scorpio console
command is detailed in the following sections. The following are the
general rules:
o All commands must be abbreviated to the first letter and must be
the first character after the prompt(>>>).
o All unsupported commands and illegal characters are echoed as <BEL>
and ignored.
o Commands are parsed as they are typed; if an unexpected character
is typed the console echoes <BEL> and it is otherwise ignored.
o For all commands no action is taken on a command line until after
it is terminated by a carriage return. Carriage return is echoed
as <CR><LF>.
o Both upper case and lower case letters are accepted. The console
uses only upper case letters in its responses.
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CONSOLE 24 Jan 86
o Exactly one space is required as a delimiter to separate command
letters or qualifiers from addresses, data or count. Multiple
spaces and tabs in the place of a space are not valid. The Console
responds with <BEL> for multiple spaces and tabs.
o All numbers (addresses, data, count) are in hexadecimal in both
commands and responses.
o Legal qualifiers can be typed after the command letter, address,
data, or count.
o The symbolic address PSL must be abbreviated to P.
o No range checking is performed on addresses and data. Values too
big are truncated, and values too small are extended on the left
with zeros.
o All unrecognized control characters are echoed as <BEL> and
ignored.
o Unless specified otherwise, commands can be aborted by control-U or
control-P, responses can be aborted by control-P, and the
transmission of responses can be stopped by control-S and
re-enabled by control-Q.
In the following section the syntax for each individual command is
given.
NOTE: Items enclosed in square brackets ([ ]) are optional.
7.3.2.1 BOOT Command -
B[<qualifier>] [<DDXN>]<CR>
The B(oot) command loads the GPR's (R3 and R5), initializes the
system (processor and Bus), searches for a 64K block of good memory,
and if a 64K Block of good memory is found it starts running VAX boot
code from the Packet Buffer RAMs.
Qualifier: /R5:<data>
The <data> is loaded into GPR 5.
The qualifier is optional. If not specified,
GPR 5 is loaded with zero.
The device specification for BOOT command is of the form:
'DDXN', where
'DD' the device mnemonic,
'X' the BI node number,
'N' the unit number
The device specification is optional, and if specified, all four
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CONSOLE 24 Jan 86
characters must be typed; otherwise the console appends leading
zeros and attempts to execute the command. The device specification
typed, with all letters converted to upper case, is passed through
GPR 3. If the device specification is not typed, then 0000 0000
(HEX) is loaded into GPR3 and the default device specification is
used.
In addition the microcode performs system initialization and searches
for a page aligned 64K block of good memory; if a 64K block of good
memory is found, its starting address plus 200 (hex) is loaded into
the SP and control is transferred to VAX boot code in the Packet RAM
at 2009 0104(hex). (The VAX boot code is copied to the Packet RAM as
part of Processor Initialization).
If no page aligned 64K block of good memory is found, the console
responds with an error message code 44 (hex), corresponding to 'cant
find 64k Block of good memory', and prompts for the next command.
The GPR's are loaded with data as specified in section 4.2.
Examples:
>>>B<CR> (Boot using the default device,
R3 is loaded with 0000 0000 (hex) and
R5 is loaded with 0)
>>>B/R5:10 dda2 (ASCII equivalent of 'DDA2'
(4444 4132) (hex) is loaded into GPR 3.
Data 10 (hex) is loaded into GPR 5.)
7.3.2.2 CONTINUE COMMAND -
C<CR>
The C command begins instruction execution at the address specified
by the PC (Program Counter).
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7.3.2.3 DEPOSIT COMMAND -
D[<qualifiers>] <address>[<qualifiers>] <data>[<qualifiers>]<CR>
The D command deposits the data into the address specified.
The qualifiers can be typed at any position shown above, and they
specify the data size and the address space.
The following qualifiers are legal:
Data Size:
/B - the data size is byte.
/W - the data size is word.
/L - the data size is longword.
Address Space:
/P - the address space is physical memory; size qualifiers
B, W or L can be used.
/V - the address space is virtual memory. If memory mapping is
not enabled virtual address is treated as physical address;
size qualifiers B, W or L can be used.
/I - the address space is the set of internal processor registers
that can be addressed by MTPR and MFPR instructions.
For this qualifier the size is always Long and default
size is set to Long; any specified size qualifier is ignored.
/G - the address space is general purpose register set R0 through
R15. For this qualifier the size is always Long and default
size is set to Long; any specified size qualifier is ignored.
/E - the address space is the options section of the EEPROM. Using
the /E qualifier, 24 locations within the EEPROM can be
accessed. The specified address must be in the range of 0 to
| 17 (hex), or an error message code (49 hex) is typed. The 24
| bytes that can be accessed are:
00-02 Reserved for future use.
| 03 RX50 disable
| 04 unused
| 05 unused
06 UART0 baud rate
07 Fchip, BTB, and cache disables
| 08-17 Boot devices and addresses (Rev A1 modules only; unused
| on modules with 2 EEPROMS)
For this qualifier, the data size is Byte and default size is
set to Byte; any specified size qualifier is ignored.
/M - the address space is the set of CPU internal registers
(64 in number) in the Mchip.
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CONSOLE 24 Jan 86
| This qualifier is only legal with the E(xamine) command. It can't be
| used with the D(eposit) command.
For this qualifier the size is always Long and default size
is set to Long. Any specified size qualifier is ignored.
Access to these registers is provided only as a
debugging facility. A list of Mchip CPU registers and
their addresses can be found in the 'M-CHIP FUNCTIONAL SPEC'.
NOTE
The action of the Console when certain CPU registers are
accesssed in the Mchip using the /M qualifier is
UNPREDICTABLE.
For all other qualifiers the console responds with a <BEL> and
ignores the qualifier character.
The qualifiers are optional. If no qualifiers are specified the
default address space is physical memory, address is 0000 0000, and
data size is Long under the following conditions; after processor
initialization, immediately after entering console mode, and after
N(next) commands. Otherwise the defaults are the last address space
and data size used in the last D or E command (the address and data
must be specified for the D command).
For the D command both address and data must be specified, otherwise
| the console responds with an error message code 44(hex) corresponding
| to 'UNRECOGNIZED COMMAND' and prompts for another command.
The <address> can be the symbolic address 'P' for PSL. When the
symbolic address 'P' is used, the data size is long and the default
data size is set to long; any specified data size qualifier is
ignored. The default address is set to PSL for a subsequent E
command.
When the symbolic address 'P' is used, specification of any address
space qualifier is illegal and the console response is UNPREDICTABLE.
NOTE
The data deposited to the PSL is not checked for any context
and may leave the processor in an UNPREDICTABLE state if
program I/O mode is entered.
When the address space is specified as EEPROM locations (/E
qualifier), after depositing the data (byte) at the specified EEPROM
location, the console microcode waits for 10 milliseconds to allow
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CONSOLE 24 Jan 86
completion of the EEPROM write operation by the hardware. Note that
if the front panel switch is not in the EEPROM 'UPDATE' position, the
EEPROM is not written. Console microcode detects this situation by
reading the same EEPROM location and comparing against the write
| data. If data read from the EEPROM location does not match the write
| data, an error code 47(hex) is printed on the console.
7.3.2.4 EXAMINE COMMAND -
E[<qualifiers>] [<address>][<qualifiers>]<CR>
The E command reads from the <address>, using the address space and
size qualifiers, and then prints the address space letter, address,
and data.
The 'qualifiers' shown above can be typed in any order. The
'qualifiers' and their defaults are the same as for the D(eposit)
command.
When the address space is specified as virtual memory (/V), if memory
mapping is enabled, the translated physical address is printed.
The <address> is optional. The default address is the last address
size used plus the last data size used in the last D or E command.
It is plus 0 after processor initialization, N(next) commands, and
after immediately entering console mode.
After a processor 'double error' halt, the command E/M <address> can
be used to obtain a copy of the stack stored in the CPU's Mchip
registers. The contents of these registers for various conditions of
machine check are provided in the Machine Check Section.
NOTE
For an E/M command with an address of 2C(hex), the console
responds with the Mchip's copy of the PSL, which contains
zeroes for PSL Condition Codes and TP.
EXAMPLES:
1.
>>>E/L/P 1234<CR>
Console response for an address of 1234(hex) containing
data 1234 5678 (hex),
P 00001234 12345678
>>>
2.
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CONSOLE 24 Jan 86
>>>E 1234/W/P<CR>
CONSOLE RESPONSE:
P 00001234 5678
>>>
3.
>>>E/P 1234/B<CR>
CONSOLE RESPONSE:
P 00001234 78
>>>
4. Assuming the Virtual address 0001 1234(hex) is mapped to
physical address 1234(hex) and memory mapping is enabled,
for
>>>E/L/V 11234<CR>
the Console Response is:
P 00001234 12345678
>>>
5.
>>>E P<CR>
CONSOLE RESPONSE:
03C00004
>>>
6.
>>>E/G 7<CR>
CONSOLE RESPONSE:
G 00000007 12345678
>>>
7.3.2.5 HALT COMMAND -
H<CR>
The halt command does not affect the processor. The <control>P typed
to enter console mode from program I/O mode halts the processor and
this command is a 'NOP' for backward compatibility with other VAXes.
No action other than printing the contents of the PC is taken.
EXAMPLE:
>>>H<CR>
Console Response:
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CONSOLE 24 Jan 86
PC = 00000204
>>>
7.3.2.6 INITIALIZE COMMAND -
I<CR>
The initialize command causes the Processor initialization. The I
command doesn't affect any other BI nodes. A detailed list of
processor resources initialized is given in the initialization
section.
7.3.2.7 NEXT COMMAND -
N<CR>
The N command executes one VAX macroinstruction at the address
currently contained in the PC and prompts.
EXAMPLE:
>>>N<CR>
Console response after the execution of one VAX instruction:
PC = 00001240
>>>
7.3.2.8 START COMMAND -
S [<address>]<CR>
The S command starts execution of macro instructions at the specified
address. No Initialization is performed. The S command is
equivalent to a D(eposit) to the PC followed by a C(ontinue).
The <address> is optional. The default macroinstruction address is
whatever may be currently in the PC.
7.3.2.9 TEST COMMAND -
T[qualifier]<CR>
qualifier: /M - menu driven Customer Runnable Diagnostics (CRD).
The T<CR> command executes the slow self-test. In response to the
T<CR> command, the console microcode sets RESET in the PCNTL CSR to
assert BI RESET L. This starts an ACLO - DCLO powerdown/up sequence
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CONSOLE 24 Jan 86
and forces the microaddress to 0000. The results of the selftest are
printed on the console. For a complete description of the selftest
see Selftest section. If the selftest fails, an error code 40(hex)
meaning 'self-test failed' is printed on the console. If the
self-test is successful, the following additional steps are
performed:
1. Load Patches from the EEPROM.
2. Powerup (system) Initialization
3. Load BI memory starting and ending addresses
And the console then prompts for the next command.
A sample output to the console during selftest is given in the last
sub-section of this section.
T/M<CR> is the command to load the menu driven CRD supervisor. This
command is equivalent to typing B/R5:11<CR>. See the boot comand
sub-section.
During a T/M<CR> command, the console loads 11(hex) into R5, 0 into
R3, performs a system initialization, searches for a page aligned 64K
block of good memory, and passes control to the VAX boot code in the
packet RAM at physical address 2009 0104 (hex). No KA810 module
selftest is performed during the T/M command.
7.3.2.10 XFER COMMAND -
X[<Qualifiers>] <address> <count><CR><checksum>
The X command reads or writes the specified number of bytes to
physical memory starting at the specified address.
Qualifiers:
/P - is an optional qualifier since physical memory is also
the default. It is used for backward software
compatability
NOTE
Writes to the EEPROM are not supported by the X command. The
result of writing to the EEPROM using the X command is
UNPREDICTABLE. Twenty four customer configurable locations
in the EEPROM can be written however, by using the D command
with the /E qualifier, as explained by the /E qualifier of
the Deposit Command Section.
The default address qualifier is physical memory.
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CONSOLE 24 Jan 86
<address>: starting physical memory address or control store address.
<count> : number of bytes to read or write, as indicated by bit <31>
of the count:
bit <31> = 0 write.
bit <31> = 1 read.
The remaining bits are treated as a positive number.
<checksum>: command checksum.
NOTE
When the operation is a write, i.e. bit <31> = 0, the input
data bytes are not echoed.
The console accepts the command upon receiving the carriage return,
<CR>. The next byte the console receives is the command checksum,
which is not echoed. The command checksum is verified by adding all
command characters, including the terminating carriage return and the
checksum, into an 8 bit checksum register which is initialized to
zero. If the result is zero the checksum is correct. If the
| checksum is correct the console prompts and sends data or receives
| data. If the command checksum is incorrect, error code 48(hex)
corresponding to "BINARY TRANSFER CHECKSUM ERROR" is sent.
X command for accessing physical memory:
If the qualifier is /P or if none is specified, the access is to
physical memory.
If bit <31> of <count> is clear, it is a write to physical memory.
If the command checksum is correct, the console responds with the
input prompt and accepts the specified number of bytes to deposit
into the physical memory and an additional byte of received data
checksum. Note that the data being deposited and the checksum byte
are not echoed. The received data is verified by adding all the data
bytes and the data checksum into an 8 bit register that is initially
set to zero. If the result is non-zero the data or checksum is
incorrect. If the data checksum is correct the console prompts for
| the next command. If the data checksum is incorrect the console
| responds with an error code 48(hex) and prompts as shown:
?4A
>>>
If bit <31> of <count> is set, the operation is a read from physical
memory. The console responds with the prompt followed by the
specified number of bytes from physical memory, starting from the
specified address and an additional byte of data checksum. The data
checksum is obtained by adding each byte being sent into an 8 bit
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CONSOLE 24 Jan 86
register that is initially set to zero; the 2's complement of the
contents of the 8 bit register is the checksum. After transmitting
the data checksum, the console prompts for the next command.
During a binary read from physical memory, control characters
<control>P, <control>S and <control>Q can be used to control the
console response.
Console microcode does not interpret the characters received during
command checksum input and during write to physical memory or
microcode memory, so control characters ^S, ^Q, ^P, ^U have no
effect.
7.3.2.11 Z (BI FORWARD) COMMAND -
Z <num><CR>
<num>: BI node number, one HEX digit 0 to F, to which
characters are to be forwarded. If more than
one Hex digit is typed, only the last hex digit
is used.
NOTE
If the specified node does not implement an RXCD register, a
BI error occurs. The console prints an error code 4C(hex)
and prompts.
The Z command is a V-11 specific command and is not specified in the
VAX SRM.
The Z command is meant for forwarding characters to another BI
console. The console accepts the command upon receiving <CR> and
enters the 'forwarding mode'. In this mode, characters typed at the
console, with the exception of <control>P and <ESC>, are forwarded to
| the specified BI node. The specified node echoes all the characters
| that it receives. The receiving node can receive characters from a
| third node, but it always echoes to the node specified within its
| EEPROM.
The console treats the two characters, <control>P and <ESC> in a
special manner. Unless immediately preceded by an <ESC> character,
<control>P is not forwarded and causes the local console to terminate
the forwarding mode and prompt for the next command. The <ESC>
character provides a means of forwarding a <control>P to the
specified BI node. When an <ESC> is typed, the local console
forwards the next character typed - even if it is a <control>P or
another <ESC>. Thus, for the input sequence:
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CONSOLE 24 Jan 86
<ESC><^P> - ^P is forwarded.
<ESC><ESC> - the first <ESC> causes the second <ESC> to be
forwarded
A flow chart of the execution of Z command is shown in fig. 7.2.
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CONSOLE 24 Jan 86
.---------------.
|Z COMMAND EXEC | At the Primary Processor
`-------+-------'
.---->------------------->|
| V
| NO .------------------------------.
| .<-----| CHAR FROM PHYS. CONSOLE ? |
| | `----------+-------------------'
| | | YES
| | .-------+-------. YES
| | | CHAR = ^P ? |----------------->------------------.
| P| `-------+-------' |
| O| | |
| L| V NO |
| L| .----------------. YES |
| | | CHAR = <ESC> ? |--------------->-. |
| F| `--------+-------' .---------+-----------. |
| O| V NO |GET NEXT CHAR TO FWRD| |
| R| | `---------+-----------' |
| | |<------------------------' |
| C| .----------+---------. |
| H| | SET 1 SECOND TIMER | |
| A| | START TO FWRD CHAR | |
| R| `---------+----------' |
| | | |
| F| .--------+--------. |
| R| | READ DEST. RXCD | |
| O| `--------+--------' REPOLL EVERY 1 MSEC |
| M| |<---------------------------------------. |
| | .-----+----. NO .-----------------. | |
| | R| | READY ? |----------->| 1 SECOND OVER ? +----' |
| | E| `-----+----' `--------+--------' |
| | M| YES |<-------------------------' YES |
| | O| V |
| | T| .-------+-----------. |
| | E| | WRITE DEST. RXCD | |
| | | `---------+---------' |
| | N| | |
| | O| .-------+-------. |
| | D`--------->| READ OWN RXCD | POLLING FOR RESPONSE |
| | E `-------+-------' OR ECHO |
| | | |
| | NO .---+----. |
| |<--------------------| CHAR? | BUSY BIT SET? |
| | `---+----' |
| | | YES V
| | .---------------------. .-----------.
| | |PRINT CHAR ON CONSOLE| | PROMPT |
| | `---------+-----------' `-----------'
`<------------------------'
FIG. 7.2 CONSOLE Z COMMAND EXECUTION FLOW.
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CONSOLE 24 Jan 86
The specified BI node can be put into console mode by typing
<ESC><control-P>. After receiving the prompt from the specified
node's console, other console command characters can be forwarded.
| NOTE: If the console microcode detects that the remote node is busy,
| (BUSY = 1) for more than 1 second while attempting to forward a
| character, console microcode overwrites the character in the remote
| node's RXCD with the new character.
7.3.2.12 ! (COMMENT) -
![<ch><ch> ..]<CR>
The comment command echoes the characters typed after !. No Other
action is taken by the console.
7.3.2.13 CONTROL CHARACTERS AND CR (CARRIAGE RETURN) -
The SCORPIO console supports control characters <control>P,
<control>S, <control>Q, and <CR>(carriage return) when in console
mode. All other control characters are echoed as <BEL> and ignored.
1. <Control>P is echoed as "^P". <Control>P causes the console to
abort the processing of the current command. <Control>P typed
during a 'Z' command aborts the forwarding mode and prompts for
the next command. <Control>P also clears a prior <control>S.
When typed as a part of a command line, the console deletes the
command line as it does with <control>U.
2. <Control>S stops all console transmission to the console terminal
until <control>Q is typed. Additional input between <control>S
and <control>Q is not buffered and is thrown away. Any
additional <control>S' before the <control>Q are ignored.
<Control>S is not echoed.
3. <Control>Q re-enables the output stopped by a <control>S.
Additional <control>Qs are ignored. <Control>Q is not echoed.
4. <Control>U deletes the entire command line and prompts for the
next command. <Control>U is echoed as "^U". When typed on an
empty line, <control>U is echoed and is ignored. The console
then prompts for the next command.
5. Carriage return terminates a command line. No action is taken on
the command line until it is terminated by the <CR>. Carriage
return is echoed as <CR><LF> (carraige return, line-feed). <CR>
on an empty line causes the console to reprompt.
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CONSOLE 24 Jan 86
NOTE
Control characters <control>P, <control>S and <control>Q
have no effect during the binary load of an X command.
They can however be used to control the console output
during the binary unload of an X command.
6. <ESC> is used in the Z command to forward the next typed
character without interpretation. In all other cases <ESC> is
not used. <ESC> is not echoed during a Z command; in all other
cases it is echoed as <BEL>.
7.3.2.14 <BREAK> - CONSOLE AUTOBAUD - When the processor is in
console mode, the <BREAK> key can be used to correct the baud rate of
the physical console's serial line, which is UART0 in the Mchip.
This feature is V-11 specific and is not specified in the VAX SRM.
For each <break> character that's typed, console microcode increments
the programmable baud rate to the next higher speed, (150, 300, ..
19200, 150 .. etc.) In order to give a visual indication that the
<BREAK> command was received, the RUN light is turned on momentarily,
for about 250 milliseconds. This verifies the input path to UART0.
In addition, console microcode prints the following output on the
console terminal:
<CR><LF>
>>>
This output provides a visual check for the baud rate. If the above
characters appear garbled, then the baud rate does not yet match;
when the output appears as shown above the baud rate matches that of
the console terminal.
NOTE: 1. This feature can be used only for UART0 when the
Processor is in Console mode.
2. The console aborts the input of a command line,
parsing a command or execution of a command upon
detecting a <BREAK>.
3. The baud rates are: 150, 300, 600, 1200, 2400, 4800,
9600, and 19200.
4. Both transmit and receive baud rates are set to the
same value.
5. Note that the default baud rate in the EEPROM is not
modified.
6. <BREAK> can not be forwarded to a remote BI console.
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CONSOLE 24 Jan 86
7.3.3 SCORPIO CONSOLE RESPONSES - The SCORPIO console terminal is used
to print information during:
1. Restart to indicate the reason (Halt codes),
2. Console mode for Error reporting and command responses.
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7.3.3.1 HALT CODES - Except when the halt was requested by a console
Halt command or Next command, the console responds with "?" followed
by a halt message in the form of the following halt codes with the
contents of the PC (program counter).
HALT CODE MEANING
--------- -------
?00 Not used (Never generated)
?01 NOT USED
?02 CPU halted
A control-P was received from the enabled source (UART0
or BI node) while the processor was in program I/O mode
and the console was enabled, which halted the processor.
?03 Power fail restart
NOTE: this code is not printed; it is passed on to the
Operating System.
?04 Interrupt Stack not valid - in attempting to push state
onto the interrupt stack during an interrupt or exception,
the processor discovered that the interrupt stack was
mapped as NO ACCESS or NOT VALID.
?05 CPU Double Error - the processor attempted to report
a machine check to the operating system, and a second
machine check occurred.
?06 Halt executed - the processor executed a halt instruction
while in kernel mode.
?07 Invalid SCB vector - the vector had bits <1:0> set.
?08 No user WCS - there is no user WCS on SCORPIO.
?09 Not used.
?0A CHM from interrupt stack - a change mode instruction
was executed when PSL <IS> was set.
?0B CHM to Interrupt stack - the exception vector for
a change mode instruction had bit <0> set.
?0C SCB read error - a hard memory error occurred while
the processor was trying to read an exception or
interrupt vector.
?0D A BOOT message was received over the NI.
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CONSOLE 24 Jan 86
EXAMPLE: Upon executing a HALT instruction in kernel mode with the console
switch in the HALT position, the following information is printed on the
console:
?06
PC = 00000200
>>>
7.3.3.2 RESPONSES FROM CONSOLE MODE - The console prompt is ">>>".
All responses of the console use uppercase letters and hexadecimal
digits. Several examples of console responses to commands can be
found in their descriptions. In this section, the error codes the
console uses are given.
The SCORPIO Console uses two digit codes for error reporting. The
error codes are preceded by a ?. EXAMPLE: When the console
encounters a command that it can't recognize, the error message code
corresponding to "UNRECOGNIZED COMMAND" is printed as:
?44
>>>
The various error messages are provided in the following table.
SCORPIO CONSOLE ERROR CODES AND MESSAGES
ERROR
CODE(HEX) MEANING
------- ------------------------------------------
|
| ?40 Selftest failed at Power-up.
|
| ?41 ACLO timeout.
|
| ?42 Restart/Cold Boot failed; cold start flag was set.
|
| ?43 Can't find 64K block good memory while attempting
| a Cold restart in response to a B command, or when
| the Warm start failed
|
| ?44 Unrecognized Command, the console can not execute
| the command as typed, or there is an invalid boot
| device specicification.
|
| ?45 Memory reference not allowed. An A, D, or E command
| required a memory reference and a TNV (translation
| not valid) or ACV (access violation) occurred.
|
| ?46 Illegal Access of an IPR. The specified IPR of the
| D or E command can not be accessed.
|
| ?47 The address specified by the D/E or E/E command was
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CONSOLE 24 Jan 86
| outside the valid range of 0 to 17 (hex),
| or,
| a write to the EEPROM was inhibited. The read-check-
| after-write, in response to a D(eposit) to the EEPROM
| failed.
|
| ?48 Incorrect Checksum of command or data during an X
| command.
|
| ?4A Error while loading the primary patches from the EEPROM.
|
| ?4B Checksum error on the boot file in the second EEPROM,
| (only possible in modules with 2 EEPROMs).
|
| ?4C Hardware Error which can be caused by a MIB or DAL
| parity error, or a detected BI Error, or from non-
| existent memory or device.
|
7.4 APT SUPPORT
There are no specific commands, microcode, or hooks in the Scorpio
console for APT, but there is nothing that should preclude the use of APT
in manufacturing. The following commands and setup can be used for APT:
1. UART0 is the physical console and APT can be connected to UART0. On
power-up the console uses the default baud rate from the EEPROM;
since APT requires a 19200 baud rate, the default baud rate can be
set in the EEPROM to 19200.
2. The commands C, D, E, I, S and X can be used for communication by
APT.
3. The console always echoes legal characters.
4. During an X command load, input data bytes and data checksum are not
echoed.
5. An APT software driver would be required in order to use APT for the
Scorpio system.
7.5 CONSOLE OUTPUT DURING BOOTING
This section summarizes the outputs to expect from the various boot
paths.
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EXAMPLE 1) Power-up
Slow selftest enabled and no errors.
BI Nodes 0,1,2,3, and 5 have devices.
BI memory of 00800000 hex bytes.
Reboot enabled.
Good memory in system.
#ABCDEFGHIJKLMN#
0 1 2 3 . 5 . . . . . . . . . .
00800000
<control passed to VAX macrocode>
EXAMPLE 2) power-up
Slow self-test enabled and no errors.
BI Nodes 0,1,2,3, and 5 have devices.
BI node 5 is broken.
BI memory of 00800000 hex bytes.
REBOOT enabled
Good memory in system.
#ABCDEFGHIJKLMN#
0 1 2 3 . -5 . . . . . . . . . .
00800000
<control passed to VAX macrocode. WARM start is disabled>
EXAMPLE 3) power-up
Slow self-test enabled and IE CHIP.
#A-
?40
PC = aaaaaaaa ! current PC
>>>
EXAMPLE 4) FAST selftest enabled.
BI Nodes 0,1,2,3, and 5 have devices.
BI memory of 00800000 hex bytes.
Reboot Enabled
##
0 1 2 3 . 5 . . . . . . . . . .
00800000
<control passed to VAX macrocode>
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EXAMPLE 5) VAX error halt or HALT instruction.
REBOOT enable
Good memory in system.
?xx ! reason for halt
PC = aaaaaaaa ! current PC
<control passed to VAX macrocode>
EXAMPLE 6) VAX error halt or HALT instruction
REBOOT enabled but fails.
?xx !reason for error halt
PC = aaaaaaaa ! current PC
?42 ! restart/reboot failed.
PC = aaaaaaaa ! current PC
>>>
EXAMPLE 7) VAX error halt or HALT instruction
REBOOT disabled.
?xx ! reason for error halt
PC = aaaaaaaa ! current PC
>>>
EXAMPLE 8) <control>P from ENABLED console source.
?02 ! halt because control-P
PC = aaaaaaaa ! current PC
>>>
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EXAMPLE 9) "T" console command.
Slow self-test with no errors.
BI Nodes 0,1,2,3, and 5 have devices.
BI memory of 00800000 hex bytes.
#ABCDEFGHIJKLMN#
0 1 2 3 . 5 . . . . . . . . . .
00800000
?01
PC = aaaaaaaa ! current PC
>>>
EXAMPLE 10) "T" console command.
Slow selftest with an IEchip error.
BI Nodes 0,1,2,3, and 5 have devices.
BI memory of 00800000 hex bytes.
#A-
?40 ! Self-test failed.
PC = aaaaaaaa ! current PC
>>>
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MACHINE CHECK SPECIFICATION 24 Jan 86
8.0 MACHINE CHECK SPECIFICATION
The purpose of this part of the document is to describe how the KA820
microcode handles serious hardware and microcode related error conditions.
These conditions include:
1. TB and Cache Tag Parity Errors
2. BI Errors
| 3. Cache Data Parity Errors
|
| 4. MIB Parity Errors
5. Impossible situations in microcode
6. Unidentified IPL interrupts
7. CPU Double Error HALT
8. Errors from console mode and powerup
| 9. PCntl Timeout
|
Like other exceptions, Machine Check Exception is taken independently of
the IPL. The IPL is raised to 1F. A length parameter, an error code, and
the contents of several registers, and a status word is pushed onto the
stack as longwords. Software determines, on the basis of the information
presented, whether to abort the current process, if the machine check was
| the result of the current process. The cache is invalidated during all
| microcode machine checks.
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8.1 MACHINE CHECK CONDITIONS
8.1.1 CACHE TAG PARITY ERRORS - A cache tag parity error can occur on
reads to the cache. The microcode invalidates the cache block in
question, and then takes the machine check. The Microcode then
disables the cache. It is up to the software's machine check service
routine to re-enable it for the purposes of determining whether it is a
hard error, or just a transient error. The MAR register on the stack
is valid after these errors.
8.1.2 BTB TAG PARITY ERRORS - A BTB tag parity error can occur in one
of two ways. The microcode was either doing a READ PTE operation (done
in the memory management microcode to load the BTB so a virtual to
physical address translation may take place), or it was in an MTB miss
cycle which requires a PTE to be read from the BTB. When the error
occurs, the entry in the BTB is invalidated. The machine check will
then be invoked. The microcode will NOT disable the BTB. The MAR is
also valid during these errors.
|
|
|
| 8.1.3 CACHE DATA PARITY ERRORS - Data parity errors are flagged after
| the operation that detected the error. Therefore, the address
| information is suspect.
8.1.4 BI ERRORS - BI errors are the detection of errors from the
system devices on the BI, which includes BI memory. The PCNTL
determines when there is a BI error by decoding the BI Event lines.
These BI event codes are saved to indicate the cause of the error. The
MAR may or may not contain the address that detected the error. Since
BI write transactions are pipelined, a memory write error isn't
detected until the MAR may have been updated with the following
transaction address. A bit in the PCntl is saved to indicate when the
error was due to a write. For errors in I/O space, the address
information is valid.
8.1.5 MIB PARITY ERRORS - MIB PARITY ERRORS can be control store
parity, or transmission errors. Since these conditions may be
transient, the microcode will perform a 'NOP' loop for 200 microseconds
before proceeding.
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8.1.6 IMPOSSIBLE MICROCODE SITUATIONS - The microcoder believes that a
set of conditions cannot happen and it has just happened (i.e. alu.n
and alu.z are both set as a result of an alu operation). The parameter
sent to machine check is a reference to the condition.
8.1.7 INTERRUPT AT AN UNIDENTIFIED IPL - The VAX architecture provides
a range of IPLs, and the KA820 uses a subset of these. If an interrupt
occurs at one of the levels not used, the VAX CAN'T RESTART bit is
cleared, and a machine check is taken.
8.1.8 CONSOLE AND POWERUP ERRORS - Powerup microcode must perform
operations to determine the state of the machine (i.e. determine the
size of memory, if a BI memory board or other device is broken, search
for a valid RPB, etc.), and errors can occur during these operations.
Similarly, when the CPU is in console mode, errors can occur during the
execution of console commands, such as Examine and Deposit. The
machine cannot go through normal error handling routines, as there
won't be any error recovery software to handle the problem, nor an SCB
set up. During powerup and various console operations, an internal
state bit is set. This bit acts as an escape back to the
console/powerup code, preventing a VAX machine check exception.
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8.2 MACHINE CHECK EXCEPTION
Machine check microcode must perform operations in which additional
errors may occur. To prevent indefinitely looping through an error
handling routine, in which another error causes it to loop again, a
hardware fault state bit is used by the machine check microcode.
8.2.1 HARDWARE FAULT STATE BIT - When the hardware detects an error
this bit is set. When set this bit prevents subsequent error
detection. The status of hardware fault state bit is visible as a red
LED on the KA820 module. Once the parameters for the stack are
gathered, this bit is cleared, such that if there is another hard
error, machine check microcode will be be re-entered to handle the new
error.
8.2.2 MACHINE CHECK CONDITION - The MACHINE CHECK CONDITION flag
performs for the software the same function that the Hardware fault
state bit performs for the microcode. This is to prevent indefinite
loops within machine check microcode that have machine check exceptions
occur. All of the various error handling microcode first checks if the
MACHINE CHECK CONDITION flag is set. If set, it was already processing
a machine check, and control is transferred to the CPU Double Error
Halt handling microcode. When entering the error handling microcode,
the MACHINE CHECK CONDITION flag is set, which indicates that it is
processing a machine check.
The microcode will also attempt to turn OFF the RUN light on the front
panel. On a CPU DOUBLE ERROR the microcode will enter console mode,
display the proper error code as described in the console section, and
leave the run light off.
NOTE
It is up to the machine check macro software to clear the
MACHINE CHECK CONDITION via an MTPR to the MCESR register. If
the software clears this flag incorrectly, it is possible to
generate an infinite loop. If the first VAX instruction of the
software's machine check handler fails, a machine check trap is
taken again, which eventually clears the bit, again trys to
execute the first VAX instruction, takes another machine check,
etc...
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8.3 ERROR RECOVERY
When an error occurs during the execution of a VAX MACROinstruction,
there is a status word that is pushed onto the stack. This status word
contains information important for restarting the MACROinstruction.
NOTE
The definition of 'restartability' of VAX instructions may be
found in the VAX SRM, Rev. 7, page 8-7.
8.3.1 ERROR RECOVERY SOFTWARE CONSIDERATIONS - Once the machine check
exception is taken, it is up to the operating system or MACRO software
to determine what to do next. The items that get pushed onto the stack
are intended to be an aid to the error handler programmer. The
important thing is to try to recover only when there is no chance of
producing catastrophic results, such as wrong answers or corrupting the
system's database. The microcode for REI is written such that the only
error that may extend to another process is a MIB PARITY ERROR.
| 8.3.2 USE OF VAX CAN'T RETRY BIT - The VAX CAN'T RETRY BIT implies
| that an instruction cannot be retried. This bit may be incorrect for
| some BI errors, or when the FPD (First Part Done) bit is set.
|
For BI errors, some BI EVENT CODES say that the error was caused by
this process. These are re-tryable because the address information is
valid. However, for writes to memory or other BI EVENT CODES, the
state of the address information is unknown. It is unwise to attempt a
restart in these cases.
If the FPD bit is clear, it should have produced the same result as if
the instruction was executed for the first time.
If the FPD bit is set, then the instruction was packed up via it's own
packup routine, so it can begin execution from the 'middle' of the
instruction. If a MIB parity error occurs, the microcode state is
incomplete, therefore the packup routine could produce an incorrect
result.
The following is an attempt to summarize all of this.
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FPD= FIRST PART DONE bit; VCR = VAX CAN'T RETRY bit.
FPD = 0, VCR = 0; Depending upon the error,
the instruction may be retried.
FPD = 0, VCR = 1
or
FPD = 1, VCR = 1; This means that either memory or
a GPR was modified. Retrying the
instruction may produce the wrong
results. The operating system must
not continue this process.
FPD = 1, VCR = 0; This means that this pass thru the
instruction hasn't changed any state
and the instruction may be retried,
depending upon the error.
8.4 STACK CONTENTS DURING MACHINE CHECK
The microcode provides this information to the software's machine check
handler:
Data available Location Location in the Mchip's
in memory internal registers
---------------- --------- -------------------
Byte count (20 hex) (SP) Not needed...
Mcheck type code (SP)+4
Parameter 1 (SP)+8 MTEMPB
VA (SP)+12 MTEMP13
VA Prime (SP)+16 MTEMP.PSL.TEMP
MAR (SP)+20 MTEMP9
Status Word (SP)+24 MTEMPC
PC at failure (SP)+28 MTEMPF
UPC at failure (SP)+32 MTEMP10
PC (SP)+36
PSL (SP)+40
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MACHINE CHECK SPECIFICATION 24 Jan 86
8.4.1 BYTE COUNT - (SP) - This location tells the number of bytes that
were pushed onto the stack.
8.4.2 MACHINE CHECK TYPE - (SP)+4 - This is where the error type bits
are stored by the microcode, to provide information to the software as
to the source of the error. More than one bit may be set.
31 7 6 5 4 3 2 1 0
+-------------------------+------+------+------+------+------+------+------+
| |cache | BTB | BI | data | MIB |ucode | IPL |
| UNUSED | tag | tag |error |parity|parity|error | BAD |
| |parity|parity| | error| error| | |
+-------------------------+------+------+------+------+------+------+------+
The only mutually exclusive errors are CACHE TAG PARITY and BTB TAG
PARITY
8.4.3 PARAMETER - (SP)+8 - If UCODE ERROR is set, this is a reference
to the microcode condition. If cache tag or BTB tag parity are set,
this is the corresponding tag.
8.4.4 VA <31:0> - (SP)+12 - This is the virtual address register. It
may contain the virtual address that caused the error. It is included
for microcode debugging only.
8.4.5 VA PRIME <31:0> (SP)+16 - This is also a virtual address
register. It may contain the virtual address that caused the error.
It is also included for microcode debugging only.
8.4.6 MAR <31:0> (SP)+20 - This is the memory address register. It
may contain the physical address that caused the error.
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MACHINE CHECK SPECIFICATION 24 Jan 86
8.4.7 STATUS WORD <31:0> (SP)+24 - This status word contains useful
status bits.
|
|
| 30 29 23 22 21 20 16 15 14 12 4 3 2 1 0
| +---+---------+---+---+-----------+---+---+ +--+ +---+---+---+---+---+
| |VCR|reserved |BI |WRT| BI Event | |CA | | P| |BTB|MTB| C |PC |MAR|
| | | for SW |ERR|MEM| Codes | |DAT| | T| |TAG|MIS|TAG|ERR|LCK|
| | | | | | | |PAR| | O| |PAR| |PAR| | |
| +---+---------+---+---+-----------+---+---+ +--+ +---+---+---+---+---+
|
| All other bits are unused
|
o Bit <30> VAX CAN'T RETRY BIT - This bit is to be used by software
in determining if a VAX instruction is restartable. The bit is
CLEARed at the beginning of each instruction's execution, or at the
beginning of an instruction's restart from FPD (FIRST PART DONE).
The bit is SET by hardware when one of the following takes place:
ANY REFERENCE TO AN I/O SPACE ADDRESS
ANY SUCCESSFUL WRITE TO MEMORY
ANY SUCCESSFUL WRITE TO A GPR THAT WAS NOT
AUTO-INCREMENTED/DECREMENTED.
If the microcode specifically does not want the VAX instruction to
be retried, it sets this bit. If the bit is set, macro software
should NOT attempt to retry the instruction.
o Bit <22> BI ERROR - This bit identifies that the BI EVENT CODE and
write memory bit are valid and pertinent.
o Bit <21> WRITE MEMORY BIT - The bit is used to identify that the BI
EVENT CODE is due to a write to memory space.
o Bits <20:16> BI EVENT CODE - This field represents the status of
the previous BI transaction.
| o Bit <14> CACHE DATA PARITY ERROR - This bit is used to identify
| that the PCNTL has detected a data parity error when reading from
| the cache. This is the only information available about the parity
| error.
|
| o Bit <12> PTO - This bit is used to indicate that the PCntl has
| timed out, which implies that it sent out a request to the BI or to
| one of the PCI devices, and it didn't receive a response. After
| 12.6 msec, it times-out, clears itself, and aborts that
| transaction.
|
| o Bit <4> BTB TAG PARITY ERROR - A tag parity occurred while reading
a BTB ENTRY.
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o Bit <3> MTB MISS - The BTB read was the result of an MTB Miss
operation.
o Bit <2> CACHE TAG PARITY ERROR - A tag parity error occurred while
reading a cache location.
o Bit <1> PCNTL DETECTED ERROR - BI ERROR and/or CACHE/BTB DATA
PARITY ERROR is valid and pertinent.
o Bit <0> MAR IS LOCKED - This implies that status word bits <22:0>
are valid and pertinent.
8.4.8 PC At Failure <31:0> - (SP)+28 - This is the VAX PROGRAM COUNTER
when the error occurred.
8.4.9 UPC At Failure <31:0> - (SP)+32 - This is the micro PROGRAM
COUNTER when the error occurred.
8.4.10 PC <31:0> - (SP)+36 - This is the contents of the macro Program
Counter
8.4.11 PSL <31:0> - (SP)+40 - This is the Processor Status Longword
8.4.12 BI EVENT CODES - This section provides a list of all possible
BI event codes, which are all described in detail in the BIIC Spec.
Anytime that error handling microcode puts error information on the
stack, these bits are included in the status word (bits <20:16>) at
(SP)+24. The only time that they are pertinent however, is when the BI
error bit is also set (bit <22> of the status word).
If the BI error bit isn't set, the microcode reads these bits anyway,
which would reflect whatever is happening on the BI at that particular
time. This information wouldn't be pertinent to the error at hand.
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MACHINE CHECK SPECIFICATION 24 Jan 86
BI EVENT CODE TABLE
EVENT
CODE BI EVENT
----- ------------------------------------
0 No event (nev)
1 Master Port Transaction Complete (mcp)
2 ACK Received for Slave Read Data (akrsd)
3 BIIC Transaction Bus Timeout (bto)
4 Self-Test Passed (stp)
5 RETRY CNF Received For Master Port Command (rcr)
6 Internal Register Written (irw)
7 Advanced RETRY CNF Received (arcr)
8 NOACK Or Illegal CNF Received For INTR (nici)
9 NOACK Or Illegal CNF Received For IP INTR (nicip)
A ACK CNF Received For Error Vector (akre)
B IDENT ARB Lost (ial)
C EX VECTOR Level 4 Selected (evs4)
D EX VECTOR Level 5 Selected (evs5)
E EX VECTOR Level 6 Selected (evs6)
F EX VECTOR Level 7 Selected (evs7)
10 Stall Timeout On Slave Transaction (sto)
11 Bad Parity Received During Slave Transaction (bps)
12 Illegal CNF Received For Slave Data (icrsd)
13 Slave Transaction Aborted By Master (sabm)
14 ACK CNF Received For Non-Error Vector At Level 4 (akrne4)
15 ACK CNF Received For Non-Error Vector At Level 5 (akrne5)
16 ACK CNF Received For Non-Error Vector At Level 6 (akrne6)
17 ACK CNF Received For Non-Error Vector At Level 7 (akrne7)
18 Read Data Substitute or RESERVED Status Code Received (rdsr)
19 Illegal CNF Received For Master Command (icrmc)
1A NOACK CNF Received For Master Command (ncrmc)
1B Bad Parity Received (bpr)
1C Illegal CNF Received By The Master For Data Cycle (icrmd)
1D Master Port Transaction Retry Timeout (rto)
1E Bad Parity Received During Master Transaction (bpm)
1F Master Transmit Check Error (mtce)
This field represents the status of a previous BI transaction, and the
above list shows all possible BI Error codes. The PCntl latches these
codes on every cycle, but it only locks them into its CSR when certain
master transaction codes are detected. The following detailed
descriptions are for only those errors for which the BI Error bit will
be set
1. EVENT CODE = 03; BIIC Transaction Bus Timeout (BTO) - BI ERROR is
set. The master BI transaction is hung.
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MACHINE CHECK SPECIFICATION 24 Jan 86
2. EVENT CODE = 18; Read Data Substitute or RESERVED Status Code
Received (RDSR) - BI ERROR is set. The master BI Read transaction
has failed because the BI memory has returned data that had more
than a single bit error, making it uncorrectable. The MAR contains
the physical address of the transaction.
3. EVENT CODE = 19; Illegal CNF Received For Master Command (ICRMC) -
BI ERROR is set. The master transaction has failed because the CNF
code was incorrect. The MAR contains the physical address of read
transactions and any type of I/O transactions, but for memory write
transactions the MAR contains unreliable address bits.
4. EVENT CODE = 1A; NOACK CNF Received For Master Command (NCRMC) -
BI ERROR is set. The master transaction was NO ACKed. It may be
for trying to access a non-existent memory location or an invalid
I/O space address. The MAR contains the physical address of a
memory read transaction or any type of I/O transaction, but for a
memory write transaction the MAR contains unreliable address bits.
5. EVENT CODE = 1C; Illegal CNF Received By The Master For Data Cycle
(ICRMD) - BI ERROR is set. The master transaction has failed
because of an illegal CNF CODE received. The MAR contains the
physical address of memory read transactions or any type of I/O
transactions, but for memory write transactions the MAR contains
unreliable address bits.
6. EVENT CODE = 1D; Master Port Transaction Retry Timeout (RTO) - BI
ERROR is set. The master transaction has failed because a Retry
timeout has occurred, caused by 4096 consecutive retry
confirmations.
7. EVENT CODE = 1E; Bad Parity Received During Master Transaction
(BPM) - BI ERROR is set. The master transaction has failed because
of a transmission parity error. The MAR contains the physical
address of memory read transactions or any type of I/O
transactions, but for memory write transactions the MAR contains
unreliable address bits.
8. EVENT CODE = 1F; Master Transmit Check Error (MTCE) - BI ERROR is
set. The master transaction has failed because the master node
verifies that the data on the BI doesn't match the data that it
transmitted when it was the only driver. The MAR contains the
physical address of memory read transactions or any type of I/O
transactions, but for memory write transactions the contents of the
MAR contains unreliable address bits.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 79
SYSTEM CONTROL BLOCK VECTORS 24 Jan 86
9.0 SYSTEM CONTROL BLOCK VECTORS
The following vectors are used by the KA820 System Control Block:
EXCEPTION IPL USE
VECTORS
00 14-17 Unibus/BI interrupt
04 1F Machine check abort
08 1F Kernel Stack not valid abort
0C 1E Powerfail interrupt
10 Reserved or privileged instruction fault
14 Customer reserved instruction fault
18 Reserved operand exception
1C Reserved addressing mode fault
20 Access control violation fault
24 Translation not valid fault
28 Trace pending fault
2C Breakpoint fault
30 Not used
34 Arithmetic exception
38 Not used
3C Not used
40 CHMK
44 CHME
48 CHMS
4C CHMU
INTERRUPT
VECTORS IPL USE
* 50 14 BI Bus error interrupt
54 1A Corrected read data
58 14 RXCD (Receive data register)
5C-7C Not used
80 14 Interprocessor interrupt
84-BC 1-F Software interrupts
C0 16 Interval timer interrupt
C4 14 Not used
C8 14 Serial line #1 RX interrupt
CC 14 Serial line #1 TX interrupt
D0 14 Serial line #2 RX interrupt
D4 14 Serial line #2 TX interrupt
D8 14 Serial line #3 RX interrupt
DC 14 Serial line #3 TX interrupt
E0-EC Not used
F0 14 Console storage device (RCX-50)
F4 14
F8 14 Console terminal RX interrupt
FC 14 Console terminal TX interrupt
100-3FFC 14-17 BI defined loaded by software
| * The microcode checks for BI interrupt vectors that may be erroneously
| within the range of 04 to 4C, and changes them to vector = 50.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 80
SYSTEM CONTROL BLOCK VECTORS 24 Jan 86
The following shows the interrupt levels of the KDZ11.
Hex Level Interrupt Source
1 - F Software interrupts, level 1 - 15
10 - 13 Not used
14 BI INTR4, RXCD, IPINTR, NI, RX50,
UART0, UART1, UART2, UART3
15 BI INTR5
16 BI INTR6, ICCS - Interval timer
17 BI INTR7
18 Not used
19 Not used
1A CRD - Corrected read data
1B - 1D Not used
1E ACLO
1F Used by software, machine check,
ksnv, startup
For interrupts at the same level the priority order is as listed (i. e.
for IPL 14 BI INTR4 highest AND UART3 LOWEST). The non-programmer visible
watchdog timer (explained in the boot spec), the NI interrupt, the RXCD
console interrupt, and the UART0 receive interrupts are unmaskable by the
IPL. With the exception of the watchdog timer, they are are rescheduled by
ucode to level 14.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 81
PCNTL CSR 24 Jan 86
10.0 PCNTL CSR
This CSR within the PCntl is used for storing status information, for
providing control to the CPU, and for interfacing to the front panel. It
is accessed via I/O address 2008 8000. Some of its contents are written on
the machine check stack during microcode error handling routines for use by
machine check software. This register is also accessable to software, and
although software can read or write the same bits as microcode, most of the
bits in the high order word are only used by microcode. The bits used by
software are mainly in the low order word.
I/O ADDRESS: 2008 8000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
| +------+------+------+------+------+------+------+------++------+------+------+------+------+------+------+------+
| |RSTRT | CNSL | CNSL | BI | BI | ENB | SELF | || WWPE | EVNT |WRITE | EVNT | EVNT | EVNT | EVNT | EVNT |
| | HLT | LOG | ENB |RESET | STF | APT | TEST | RUN || | LOCK | MEM | 4 | 3 | 2 | 1 | 0 |
| | | | | | | | PASS | || | | | | | | | |
| +------+------+------+------+------+------+------+------++------+------+------+------+------+------+------+------+
|
| 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
| +------+------+------+------+------+------+------+------++------+------+------+------+------+------+------+------+
| | |PARITY| ENB | PCNTL| CSR | CNSL | CLR | CNSL || RX | CLR | RX | CLR | IP | CRD | CLR | CRD |
| | WWPO | ERR H| PIPE | TIME | 11 | INTR | CNSL | INTR || INTR | RX | INTR | IP | INTR | INT | CRD | INTR |
| | | | | OUT | | ENBL | INTR | || ENBL | INTR | | INTR | | ENBL | INTR | |
| +------+------+------+------+------+------+------+------++------+------+------+------+------+------+------+------+
In the following descriptions, 1 represents a logical high (3 volts) and is
read as 1 by software or microcode. 0 represents a logical low (0 volts),
and is read as 0 by software or microcode.
* BIT<31> RSTRT HLT (Restart/Halt Powerup Option Bit)
1 = HALT, 0 = RESTART or AUTOBOOT.
Read Only bit by microcode. Boot microcode checks the status
of this bit to determine whether to boot or go to console mode
at powerup or after an error halt condition.
Set by front panel Powerup Mode Keyswitch under operator
control.
The status of this bit is only available to the primary CPU.
Since the panel switch only goes to the primary CPU the default
position (1) selects HALT on any attached processors in the
system.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 82
PCNTL CSR 24 Jan 86
* BIT<30> CNSL LOG (Physical/Logical Console Selection Bit)
1 = LOGICAL, 0 = PHYSICAL.
Read Only bit by microcode. Initialization microcode reads
this bit to determine the console source.
Set by KA820's position in the BI backplane; held low to the
primary processor by the system control module.
The 0 state of this bit is only available to the primary processor
to select UART 0 as a console source. The default position (1)
selects a logical console for any attached processors in the
system.
These two consoles, physical and logical, are explained further in
the Console Section.
* BIT<29> CNSL ENB (Console Secure/Enabled Selection Bit)
1 = CONSOLE ENABLED, 0 = CONSOLE SECURE.
Read Only bit by microcode. This bit is read by microcode
when a <CTRL> P is sent by the console to determine if console
mode is enabled. This allows locking the console so that
operator intervention from the console is inhibited.
Set by the Console Secure/Enable Keyswitch on the front panel.
This signal only goes to the primary processor to enable or
disable its console based upon the position of the keyswitch. The
default position is high on any attached processors in the system
which always enables their logical consoles.
* BIT<28> BI RESET (System Reset Control Bit)
Read/Write bit by microcode or software.
Cleared by DCLO at powerup or by DCLO as a result of the bit
being set.
Written with a 1 by console microcode during the console T
(selftest) Command. Can also be written with a 1 by software
to completely reset the system. Setting this bit creates a
power up sequencing of the BI ACLO and DCLO signals by the
system control module.
Writing with a 0 clears this bit, but it has no effect because
whenever it gets set, the resulting DCLO clears it.
This bit is buffered by an external open collector driver which
drives BI Reset L when it is written with a 1. This signal goes
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 83
PCNTL CSR 24 Jan 86
to the system control module and generates a power off/power up
sequence by driving the ACLO and DCLO signals. This in turn
causes the entire system to get reset by DCLO, including BI
memory. The self test and powerup initialization is then
initiated when DCLO is deasserted.
* BIT<27> BUF BI STF (Selftest Fast/Slow Selection Bit)
1 = FULL SELF TEST, 0 = FAST SELF TEST.
Read Only bit by microcode. Read by selftest microcode to
determine whether to run the full selftest or just an
initialization routine.
State is controlled by BI STF L.
This bit is a buffered version of the BI STF L (Self Test Fast)
line that is set by a switch on the system control module. The
purpose of this bit is to allow bypassing a 10 second powerup
selftest due to a power glitch in a real time system.
* BIT<26> ENB APT (APT Connection Status Bit)
1 = APT NOT CONNECTED, 0 = APT LINE CONNECTED.
Read Only bit by microcode.
Can be grounded by an APT line when connected to serial line
0; default position is high when nothing is connected.
Currently this bit is designed into the PCntl as a contingency so
that microcode can read the bit to determine if an APT line is
connected. It is made available for grounding when an APT line is
connected to UART0.
* BIT<25> SELFTEST PASS H (Selftest Status Bit)
1 = SELFTEST PASSED, 0 = SELFTEST FAILED, OR STILL IN PROGRESS.
Read/Write bit by microcode.
Written with a 1 by self test microcode at the end of a
successful self test, either at powerup or from the console T
(Test) command.
Cleared by DCLO at powerup.
Not written to a 0 by microcode.
This bit also has as complimentary outputs from the PCntl,
SELFTEST PASS H and BI BAD H.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 84
PCNTL CSR 24 Jan 86
When cleared by DCLO the BI Bad H output drives an external open
collector buffer that asserts BI Bad L. Selftest Pass H is
simultaneously deasserted which turns of the LED driver for the 2
yellow Self Test Passed LEDs on the module.
When written to a 1 at the conclusion of selftest, BI Bad L is
deasserted and Selftest Pass H is asserted which turns on the LED
driver for the the 2 yellow Self Test Pass LEDs.
* BIT<24> RUN L (Program Mode Run Bit)
1 = PROGRAM MODE, 0 = CONSOLE MODE.
Read/Write bit by microcode, not normally read however.
Cleared by DCLO at powerup.
Written with a 1 by microcode to indicate when the CPU is in
program mode.
Written with a 0 by microcode when going into console mode.
It is also buffered on the module and when asserted it drives PNL
RUN LED L to light the RUN indicator on the front panel.
Note: This bit is read as a 1 when written to a 1, and read as a
0 when written to a 0. Its output voltage is opposite in polarity
however, to drive the LED. (i.e. Writing the bit to a 1 causes
the output voltage to be low, and vice versa).
As an aid in troubleshooting a "dead" console terminal (i.e. no
printouts or characters echoed); the console microcode toggles
this bit each time it recognizes an ASCII T character (T = console
Test command). In turn the RUN light flashes to indicate that at
least input characters are being received and recognized by the
CPU. This implies that the problem is somewhere in the output
path to the terminal or in the terminal itself.
|
| * BIT<23> WWPE (Write Wrong Parity, Even bytes)
|
| 1 = FORCED WRONG PARITY GENERATION, AND PARITY CHECKING DISABLED
| ON THE EVEN DATA BYTES (bytes 0 and 2) OF THE CP DAL LINES.
|
| 0 = NORMAL PARITY GENERATION, AND PARITY CHECKING ENABLED ON THE
| EVEN DATA BYTES.
|
| Read/Write bits by microcode or software.
|
| Cleared by DCLO at powerup.
|
| Selftest microcode writes 1 to this bit to write bad parity
| and/or disable parity checking by the even byte data path gate
| array. Diagnostic software can do the same.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 85
PCNTL CSR 24 Jan 86
| Selftest microcode writes 0 to this bit to re-enable normal
| parity generation and parity checking by the even data path
| gate array. Diagnostic software can do the same.
|
| Written with a 1 by diagnostic microcode or software to force
| writing bad parity to either the cache or BTB parity RAMs on write
| operations. This also disables the even data path gate array of
| the PCntl from generating a parity error signal to the control
| gate array.
|
| Written with a 0 to resume normal parity generation and checking
| by the even data path gate array. Note: The equivalent odd byte
| Write Wrong Parity bit <15> is written at the same time to enable
| parity across the whole longword
* BIT<22> EVENT LOCK (Event Code Error Bit)
Read/(Write 1 to clear) bit by microcode and software.
Cleared by DCLO at powerup.
Set to a 1 whenever an error condition is detected by the
PCntl on the Event Lines from the BIIC. Once set bits <20:16>
are latched and don't reflect the state of the BIIC Event
Lines until this bit is written with a 1 to clear it.
Written with a 1 to unlock the latched event codes in CSR bits
<20> through <16>. It also unlocks the latched Write Memory
bit <21>.
Writing with a 0 has no effect.
* BIT<21> WRITE MEMORY (Memory Write Transaction Status Bit)
1 = ERROR IN WRITE OPERATION, 0 = ERROR IN-NON WRITE OPERATION.
Read Only bit by microcode.
Not initialized by DCLO.
Error detection microcode reads this bit, along with bits
<20:16>, to write to the Machine Check Stack after detecting
an error.
This bit is used for associating BI errors with pipelined BI
memory write transactions, since the error may not be detected
until the PCntl is involved with a subsequent transaction.
It is set by the PCntl during memory write transactions, two
cycles after RAK (Request Acknowledge) is asserted by the BIIC.
This allows getting past any errors that may occur due to any
prior BI transactions. It remains set as long as memory write
transactions are performed, and is only cleared when another type
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 86
PCNTL CSR 24 Jan 86
of BI transaction is initiated. As with the Event codes that
follow, this bit is locked any time an error code is detected from
the BIIC so it can be read by error handling microcode.
* BITS<20:16> EV4 through EV0 (BI Transaction Event Code Bits)
Read Only Bits by microcode.
Error detection microcode reads these bits, along with bit
<21>, and then writes them to the stack after detecting an
error.
Bit 21 indicates that a write to memory was in progress when
the error occurred.
Bits <20:16> are decoded as follows:
03 BI bus timeout
18 Read data substitute or reserved read status received
on a BI memory read
19 Illegal CNF code received for master command
1A NOACK CNF code received for master command
1C Illegal CNF code received by master for data cycle
1D Master port transaction retry timeout
1E Bad parity received during master transaction
1F Master transmit check error
These bits are latched from the BIIC by the PCntl whenever an
error code is detected. PCntl error is then asserted to the Mchip
which in turn generates Merr (Memory Error) to the I/Echip. This
causes a microtrap to error detection microcode which writes the
contents of this entire register onto the stack for machine check
software.
After being latched, the status of these bits won't change until
CSR bit <22> is written with a 1 to clear the lock.
* BIT<15> WWPO (Write Wrong Parity, Odd bytes)
1 = FORCED WRONG PARITY GENERATION, AND PARITY CHECKING DISABLED
ON THE ODD DATA BYTES (bytes 1 and 3) OF THE CP DAL LINES.
0 = NORMAL PARITY GENERATION, AND PARITY CHECKING ENABLED ON THE
ODD DATA BYTES.
Read/Write bit by microcode or software.
Cleared by DCLO at powerup.
Selftest microcode writes 1 to this bit to write bad parity
and/or disable parity checking by the odd byte data path gate
array. Diagnostic software can do the same.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 87
PCNTL CSR 24 Jan 86
Selftest microcode writes 0 to this bit to re-enable normal
parity generation and parity checking by the odd data path
gate array. Diagnostic software can do the same.
Written with a 1 by diagnostic microcode or software to force
writing bad parity to either the cache or BTB parity RAMs on write
operations. This also disables the odd data path gate array of
the PCntl from generating a parity error signal to the control
gate array.
Written with a 0 to resume normal parity generation and checking
by the odd data path gate array. Note: The equivalent even byte
Write Wrong Parity bit <7> is written at the same time to enable
parity across the whole longword.
* BIT<14> PARITY ERROR (Parity Error Status Bit)
1 = PARITY ERROR DETECTED BY PCNTL, 0 = NO PARITY ERROR DETECTED.
Read/Write 1 to clear bit by microcode.
Cleared by DCLO at powerup.
Cleared by microcode by writing with a 1.
Set to a 1 by PCntl hardware whenever a parity error is
detected on data read from the cache RAMs or BTB RAMs.
Read by error handling microcode and put on the stack along
with bits <21:16>. Cleared later by this same microcode.
When set by the PCntl, PCntl Error L is simultaneously driven to
the Mchip to cause an MERR (memory error) microtrap.
* BIT<13> ENBL PIPE H (Enable BI Pipeline Mode Control Bit)
1 = ENABLE PIPELINE MODE, 0 = DISABLE PIPELINE MODE.
Read/Write bit by microcode.
Cleared by DCLO at powerup.
Written with a 1 by initialization microcode to allow
pipelining BI transactions.
Pipeline mode keeps the PCntl from waiting until the current
transaction is completed, and confirmation received, before
posting the next BI transaction to the BIIC.
During writes to I/O space the PCntl disables pipelining, despite
the state of this bit, to assure that the transaction either
completes or an error is detected, before starting the next
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 88
PCNTL CSR 24 Jan 86
transaction. This is done for error recovery purposes. Memory
write transactions are always pipelined for performance.
| * BIT<12> PCNTL TIMEOUT
|
| 1 = PCntl timeout error occured; 0 = normal state
|
| Read/Write 1 to clear bit by microcode or software.
|
| Cleared by DCLO at powerup.
|
| Set to a 1 by hardware when the PCntl doesn't receive a response
| to a request from the BI or from any of the PCI devices. After
| each request is initiated, a timer is started which is cleared
| when the request receives a response. After 12.6 msec without
| receiving a response, this bit is set and the PCntl clears itself
| and aborts the transaction.
|
| Machine check microcode normally clears this bit.
|
| * BIT<11> CSR 11
|
| 1 = SET STATE; 0 = NORMAL CLEARED STATE
|
| Normally pulled high by hardware and read as a 0.
|
| Read only bit by microcode or software.
|
| Pin C11 on the DC348 (CSR 11 L) can be grounded and read as a 1.
| This is an extra status bit for future use which allows grounding
| to indicate some event. It can only be cleared by ungrounding.
* BIT<10> CNSL INTR ENBL (RXCD Logical Console Interrupt Enable
Control Bit)
1 = ENABLE INTERRUPTS FROM RXCD (RECEIVE CONSOLE DATA REGISTER)
0 = DISABLE RXCD INTERRUPTS.
Read/write by microcode or software.
Cleared by DCLO at powerup.
Powerup Initialization microcode sets this bit by writing to a
1 after selftest completion to enable interrupts from the
logical console.
Written with a 1 by software to enable an interrupt to be
generated to the Mchip when the Busy bit is set in the RXCD
(Receive Console Data) register.
Written with a 0 by software to disable interrupts from the
RXCD.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 89
PCNTL CSR 24 Jan 86
The RXCD is a logical console register that is used in
multiprocessor configurations; it is explained in more detail in
the Console section of this document.
* BIT<09> CLEAR CNSL INTR (Clear RXCD Console Interrupt Bit)
Write only bit (always read as 0) by microcode.
Written with a 1 by interrupt handling microcode to clear CSR
bit <8>, the console interrupt bit.
Writing with a 0 has no effect.
The logical console is covered in more detail in the console
section.
* BIT<08> CNSL INTR (RXCD Console Interrupt Bit)
1 = RXCD INTERRUPT PENDING, 0 = NO RXCD INTERRUPT PENDING.
Read only by microcode.
When set this bit generates Cnsl Intr L to the Mchip and
doesn't normally need to be read.
Cleared by DCLO at powerup.
Cleared by interrupt handling microcode by writing a 1 to CSR
bit <9>.
Set by the PCntl hardware when the Logical console is enabled
and the RXCD Busy bit is written from a 0 to a 1. This
indicates that a byte of data has been received.
| * BIT<07> RX INTR ENBL (RX Floppy Drive Interrupt Enable Control
| Bit)
|
| 1 = ENABLE INTERRUPTS FROM RX50
|
| 0 = DISABLE RX50 INTERRUPTS.
|
| Read/write by microcode or software.
|
| Cleared by DCLO at powerup.
|
| Powerup Initialization microcode sets this bit by writing to a
| 1 after selftest completion to enable interrupts from the RX50
| floppy drive.
|
| Written with a 1 by software to enable an interrupt to be
| generated to the Mchip when the RX50 is used.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 90
PCNTL CSR 24 Jan 86
| Written with a 0 by software to disable interrupts from the
| RX50.
|
* BIT<06> CLR RX INTR (Clear RX50 Interrupt Request Bit)
Write only bit (always read as 0) by microcode.
Writing with a 1 clears bit <05>, the RX50 Interrupt Request
bit.
Writing with a 0 has no effect.
Normally written by interrupt handling microcode to clear the RX50
interrupt request.
* BIT<05> RX INTR (RX50 Interrupt Request Bit)
1 = RX50 INTERRUPT REQUEST PENDING,
0 = NO RX50 INTERRUPT REQUEST PENDING.
Read only bit by microcode. This interrupt request is ORed
with IPINTR and with BI INTR4 by the PCntl, and then sent to
the MChip as BI INTR4 L. A BI INTR4 request therefore
requires the microcode interrupt handler to read this bit to
determine if it is an RX50 Interrupt Request.
Cleared by DCLO at powerup.
Cleared by microcode by writing a 1 to CSR bit <06>.
Set by the PCntl hardware whenever RX INTRA or RX INTRB pulses
are received from the RCX50 floppy disk controller. RX INTRA
is sent at the completion of each operation, and RX INTRB is
sent when the drive status changes.
This bit is normally cleared by interrupt handling microcode.
* BIT<04> CLEAR IP INTR (Clear Interprocessor Interrupt Request Bit)
Write only bit (always read as 0) by microcode.
Writing with a 1 clears bit <03>, the Interprocessor Interrupt
Request bit.
Written with a 1 by interrupt handling microcode to clear bit
<3>, the IP INTR bit.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 91
PCNTL CSR 24 Jan 86
* BIT<03> IP INTR (Interprocessor Interrupt Request Bit)
1 = INTERPROCESSOR INTERRUPT REQUEST PENDING,
0 = NO IPINTR REQUEST PENDING.
Read only bit by microcode.
Cleared by DCLO at powerup.
Cleared by interrupt handling microcode by writing a 1 to CSR
bit <04>. This is done after reading the CSR to determine the
source of the interrupt.
Set by PCntl hardware when an IPINTR request is received from
the BI. It is ORed with the RX IRQ and with BI INTR4 L. A BI
INTR4 request therefore requires the microcode interrupt
handler to read this bit to determine if it is an IPINTR
Request.
* BIT<02> CRD INTR ENBL (Corrected Read Data Interrupt Enable
Control Bit)
1 = CRD INTERRUPT ENABLED, 0 = CRD INTERRUPT DISABLED.
Read/Write bit by microcode or software.
Cleared (CRD INTR disabled) by DCLO at powerup.
Written with a 0 by software to disable CRD Interrupts.
Written with a 1 by software to enable CRD Interrupts.
Corrected Read Data Interrupts are generated by the KA820's BIIC
when single bit errors occur in the BI Memory Array and the data
has been corrected by the memory. This is normally used by soft
error logging software.
* BIT<01> CLEAR CRD INTR (Clear CRD Interrupt Bit)
Write only bit (always read as 0) by microcode.
| Must be written with a 1 by interrupt handling software to
| clear bit <0>, the CRD Interrupt Pending bit.
Writing with a 0 has no effect.
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PCNTL CSR 24 Jan 86
* BIT<00> CRD INTR (CRD Interrupt Bit)
1 = CRD INTERRUPT PENDING, 0 = NO CRD INTERRUPT PENDING.
Read only by microcode.
Cleared by DCLO at powerup.
Cleared by interrupt handling microcode by writing a 1 to CSR
bit <01>.
Set by the PCntl hardware whenever the BIIC indicates that it
has received Corrected Read Data and CRD INTR is enabled.
(Bit <02> written to a 1).
When set, CRD Intr L is asserted to the Mchip which generates an
interrupt to the I/Echip.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 93
SERIAL LINES 24 Jan 86
11.0 SERIAL LINES
11.1 RXCS1, RXCS2, RXCS3 - RECEIVE CSR REGISTERS
These 3 IPR registers are the control and status registers used in
conjunction with the UARTs for receiving characters from the serial
lines. When enabled, a received character generates an interrupt at IPL
20 in the Mchip and sets the DON bit in the appropriate RXCS register.
This implies that the UART is done receiving the character and its ready
to be read.
This results in the Mchip asserting the FPD interrupt request line to the
I/Echip. Microcode then determines whether to back out of the current
instruction, continue until completion, or continue until the FPD bit is
set, which allows interrupting in the middle of the current instruction.
Interrupt handling microcode then determines the source of the interrupt,
clears it, changes stacks, saves current state on the interrupt stack,
and gets the appropriate vector address (as shown above for each serial
line) from the system control block (SCB), to load into the memory
address register for accessing the appropriate VAX software interrupt
handler.
The VAX software driver then performs an MFPR from the RXDB register to
read the character. This instruction includes microcode which clears the
DON bit.
(R/W) RXCS1 IPR ADDRESS 50 Vector address C8
(R/W) RXCS2 IPR ADDRESS 54 Vector address D0
(R/W) RXCS3 IPR ADDRESS 58 Vector address D8
31 13 12 11 8 7 6 5 0
| +-----------------------------------+--+----------+--+--+--------------+
| | |L | |D |I | |
| | Unused |P | Unused |O |E | Unused |
| | | | |N | | |
| +-----------------------------------+--+----------+--+--+--------------+
Bits <31:14> - Unused, Read as 0's, Ignored on writes
Bit <13> LP (Loopback bit)
Read/Write bit used for diagnostic purposes to set up an internal
loopback of the UART within the Mchip. In the receiver, the UART
input is switched from the serial line input pin to the loopback bus.
All 4 serial lines can have their receive loopback bits set at one
time.
If one of the Transmitters is also in loopback mode, data that is
transmitted to that TXDB register is returned to the RXDB register(s)
that have their LP bits set. The Done bit also gets set when the
looped character is received.
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SERIAL LINES 24 Jan 86
Cleared by initialization microcode at powerup.
Write with a 1 to turn on loopback mode.
Read as a 1 when loopback mode is enabled.
Write with a 0 to disable loopback mode, reconnects
transmitter to serial line output.
Read as 0 when loopback mode is not enabled.
Bits <12:8> - Unused, Read as 0's, Ignored on writes
Bit <7> - DON (Done bit)
Read Only bit that is set whenever a character is received by the
corresponding RXDB register.
Cleared by initialization microcode at powerup
Cleared to a 0 during the MFPR instruction when a received
character is read from the corresponding RXDB register.
Read as a 1 when a received character hasn't been
read from the corresponding RXDB register.
Read as a 0 after the received character has been read by
an MFPR instruction.
Bit <6> IE (Interrupt Enable)
Read/Write bit used to enable an interrupt to be generated when a
character is received by the corresponding RXDB register. If the IE
bit is set and a character is received, or if a character was
received and then the IE bit is set, an interrupt is generated at IPL
20.
Cleared by initialization microcode at powerup
Written with a 1 to enable interrupts from associated serial line.
Read as a 1 when interrupts are enabled.
Written with a 0 to disable interrupts from being generated.
Read as a 0 when interrupts are disabled.
Bits <5:0> - Unused, Read as 0's, Ignored on writes
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SERIAL LINES 24 Jan 86
11.2 RXDB1, RXDB2, RXDB3 - RECEIVE DATA REGISTERS
These 3 IPRs are used for receiving data from serial lines 1, 2, and 3.
A software generated MFPR to read received data from these priviledged
registers results in microcode reading the equivalent UART data register
and clearing the Done bit in the appropriate RXCS register.
(RO) RXDB1 IPR ADDRESS 51
(RO) RXDB2 IPR ADDRESS 55
(RO) RXDB3 IPR ADDRESS 59
31 16 15 14 13 8 7 0
+-----------------------------------+--+--+-------------+--------------+
| |E |B | | |
| Unused |R |R | Unused | Data |
| |R |K | | |
+-----------------------------------+--+--+----------------------------+
These registers are read only, and are illegal to write.
Bits <31:16> - Unused, Read as 0's.
Bit <15> ERR (Error on received character)
The Error bit is set if the received data has an overrun, or framing
error. This bit is cleared by the Mchip upon reading this register.
Cleared by initialization microcode at powerup.
Cleared when register is read.
Read as a 1 if an error has occurred on reception of data in low byte.
Read as a 0 if the data in low byte was received without error.
Bit <14> BRK (Break bit)
Read as a 1 when a Break is received, the error bit is set to 0
during a Break. A Break is when the UART Receiver detects the 0
state for longer than 1 character transmission time. The Break bit
is also cleared by the Mchip when reading this register.
Cleared by initialization microcode at powerup.
Cleared when register is read.
Read as a 1 when a break is received.
Bits <13:8> - Unused, Read as 0's, Ignored on writes
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SERIAL LINES 24 Jan 86
11.3 TXCS1, TXCS2, TXCS3 - TRANSMIT CSR REGISTERS
These 3 IPRs are used as the control and status registers for
transmitting data via serial lines 1, 2, or 3. Whenever the associated
UART transmitter in the Mchip isn't busy, the RDY bit is set. This
indicates that the associated TXDB register is ready for another
character to be transmitted. If the Interrupt Enable bit is set when the
RDY bit is set, or if the RDY bit is set and the IE bit subsequently gets
set, an interrupt is generated at IPL 20.
The Mchip asserts the FPD interrupt request to the I/Echip, and microcode
determines whether to back out of the current instruction, continue until
completion, or continue until the FPD bit is set, which allows
interrupting in the middle of the current instruction.
Interrupt handling microcode then determines the source of the interrupt,
clears it, changes stacks, saves current state on the interrupt stack,
and gets the appropriate vector address (as shown above for each serial
line) from the system control block (SCB) to load into the memory address
register for accessing the appropriate VAX software interrupt handler.
Software can then do an MTPR to the associated TXDB register, to transmit
the next character. This results in the RDY bit being cleared until the
character is actually transmitted, at which time the RDY bit is set
again.
(R/W) TXCS1 IPR ADDRESS 52 Vector Address CC
(R/W) TXCS2 IPR ADDRESS 56 Vector Address D4
(R/W) TXCS3 IPR ADDRESS 5A Vector Address DC
31 13 12 11 9 8 7 6 5 0
+--------------------------------------+--+--+------+--+--+--+---------+
| |L |B | BAUD |B |R |I | |
| MBZ |P |R | RATE |R |D |E | MBZ |
| | |K | |E |Y | | |
+--------------------------------------+--+--+------+--+--+--+---------+
Bit <13> LP (Loopback)
The LP bit is a write only bit that is written to a 1 to enable
internal loopback mode on the UART transmitter. This is used for
diagnostics, and it disconnects the UART's output from the serial
line output pin and connects it to the loopback bus.
Note: Only one of the 4 TXCS (console SLU 0 also included) registers
in the Mchip should have their LP bit set at one time. This is to
prevent garbled data to the receiving RXDB register(s). From 1 to 4
RXCS registers may have their LP bits set at one time. This allows
from 1 to 4 of the RXDB registers to receive the loopbacked
characters.
Cleared by initialization microcode at powerup
Written to a 1 by software to enable loopback mode.
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Always read as 0.
Written to a 0 by software to disable loopback mode.
Bit <12> BRK (Break)
Write only bit that is written with a 1 to start a Break, and written
with a 0 to end the break. A Break results in the transmitter
outputting a continuous low level, for a duration of more than a full
character transmission time. Software can control the time duration
of the Break.
Cleared by initialization microcode at powerup.
Written to a 1 to start a Break.
Always read as a 0.
Written to a 0 to end a Break.
Bits <11:9> Baud Rate
Write only bits that are used to set the baud rate for that
particular UART, both receiver and transmitter. The following is a
table of the available baud rates that may be selected by setting the
BRE bit and loading <11:9> with one of the following:
Bits <12:10> Baud rate
---- ------ ---- ----
000 150
001 300
010 600
011 1200
100 2400
101 4800
110 9600
111 19200
Initialized to 1200 by powerup initialization microcode.
Written as shown above, BRE bit must also be written to a 1.
Always read as 0's.
Bit <8> BRE (Baud rate enable)
Write only bit that is set when the contents of bits <11:9> are
written with a new baud rate, for both transmit and receive for this
Uart.
Written with a 1 when setting the baud rate to the value written
into bits <11:9>.
If written with a 0, baud rate bits <11:9> are ignored.
Always read as 0.
Bit <7> RDY (Ready)
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Read only bit that is set to a 1 when the UART is ready to transmit a
character.
Read as a 1 when the TXDB register is ready to accept another
character.
Read as a 0 when the TXDB register is still trying to transmit the
character previously written to it.
Bit <6> IE (Interrupt Enable)
Read/Write bit used to enable an interrupt to be generated when the
corresponding TXDB register is ready for a character to transmit. If
the IE bit is set and the RDY bit gets set, or if the RDY bit was set
and the IE bit gets set, an interrupt is generated at IPL 20.
Cleared by powerup initialization microcode.
Written to a 1 to enable the UART transmitter to interrupt the CPU.
Read as a 1 when the TXCS is enabled.
Written to a 0 to disable the UART from generating a transmit interrupt.
11.4 TXDB1, TXDB2, TXDB3 - TRANSMIT DATA REGISTERS
(RO) TXDB1 IPR ADDRESS 53
(RO) TXDB2 IPR ADDRESS 57
(RO) TXDB3 IPR ADDRESS 5B
31 12 11 8 7 0
+--------------------------------------------+---------+---------------+
| | ID | |
| UNUSED | FIELD | DATA |
| | | |
+--------------------------------------------+---------+---------------+
These 3 IPRs are write only data buffer registers that are used to
transmit data via serial lines 1, 2, and 3. When the RDY bit is set in
the TXCS register, an MTPR instruction is used by software to write a
character to the equivalent TXDB register. It will then be transmitted
by the appropriate serial line.
Bits <11:8> ID FIELD
Write only bits that are written by microcode to distinguish between
data and console commands.
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SERIAL LINES 24 Jan 86
Written to 0000 by microcode when sending data.
Written to 1111 by microcode when sending console commands.
Illegal to read.
Bits <7:0> DATA
Write only field used to write the character to be transmitted.
Written by software with transmission data, when the RDY
bit is set in the TXCS register
Illegal to read.
Written by console microcode as follows at the same time the
ID bits are written to 1111.
2 = Boot command
3 = Clear warm start flag
4 = Clear cold start flag
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BI PROGRAMMING 24 Jan 86
12.0 BI PROGRAMMING
12.1 BI RESET
The BI has a Reset line called BI RESET L that can be driven by the
KA820. It is initiated by software writing a 1 to the PCntl CSR bit
<28>, at I/O address 2008 8000. This bit drives the BI Reset line to
each BI device in the system.
The KA820 doesn't respond to the BI Reset line, since it can only drive
the line.
12.2 BI STOP COMMAND
This command can be generated by the KA820. It is generated when
operating system software writes a mask (indicating which nodes are to
receive the STOP command) to the BISTOP privileged register (IPR 5F).
Each BI device should have the STOPEN bit of their BCI control register
set in order to receive this command. The BI Architecture Spec describes
what each node should do when it receives this command.
The KA820 doesn't respond to the STOP command, and therefore
initialization microcode doesn't set the STOPEN bit in the BCI Control
register.
12.3 BIIC REGISTERS
The BIIC is programmed by the operating system software to handle user
interrupts, error interrupts, and interprocessor interrupts. It also has
a device register and 2 control registers which are programmed. This
section explains the various BIIC registers that get initialized by
microcode and/or programmed by the operating system software.
12.3.1 REGISTER ADDRESSES - The internal BIIC registers are accessible
to software being run on the KA820 by the I/O addresses shown in fig
12.1. The microcode then uses Loopback Read and Write transactions to
access these registers. The software can also address these registers
via the BI, using the first 256 bytes of the KA820's Nodespace. This
portion of its Nodespace is termed BIIC CSR Space.
NOTE
Software running on another processor cannot access these
registers via the I/O addresses, it must use the BI node space
addresses.
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Not all of the 256 bytes of the BIIC CSR Space actually contain
registers. Most of the locations are unused. However, the BIIC
responds normally to the unused locations. When a read command
accesses the unused locations, 0's are read. When a write command
addresses the unused locations, the BIIC accepts the command, but the
data is ignored. In the register descriptions below, "bb" refers to
the base address of this node, i.e. the address of the first location
of the Nodespace.
Figure 12.1 shows a mapping of all the BIIC's internal registers, and
the following sections describe the functionality and use of the
control registers.
The BIIC does not support lock functionality for BIIC Internal
Registers. INTLK READ and UNLOCK WRITE MASK commands to internal
registers are accepted by the BIIC and treated the same as normal READ
and WRITE MASK commands, respectively. The WRITE MASK command is fully
supported for BIIC Internal Registers.
Transactions to BIIC Internal Registers (i.e. BIIC CSR Space) are
limited to a maximum length of Longword.
In the register descriptions that follow, bit characteristic codes are
used to define the nature of the register file bits. These codes are
contained in parentheses following the bit mnemonic. If all defined
bits in a register are the same type then the bit characteristics for
all register bits are shown in parentheses following the register name.
"0's" in the register diagram designate bits that are not implemented.
These bits are Read-only locations that always return "0". The
register bit characteristics are described by the following codes:
DCLOC - Cleared following a successful Self-test, initiated by the
deassertion of BI DC LO L.
DCLOL - Loaded on the deassertion of BCI DC LO L
DCLOS - Set following a successful Self-test, initiated by the
deassertion of BI DC LO L.
DMW - Diagnostic Mode Writable
STOPC - Cleared by an STOP command directed to this Node
STOPS - Set by an STOP command directed to this Node
SC - Special Case, operation defined in detailed description
RO - Read-only Bit
R/W - Normal Read/Write Bit
W1C - Write-1-to-clear Bit (User cannot set this bit)
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BI Node
Adrs I/O Adrs
31 24 23 16 15 08 07 00
+-------------+-------------+-------------+-------------+
bb+00 | Device Register | 2008 0000
+-------------+-------------+-------------+-------------+
bb+04 | Reserved | BI Control/Status Register| 2008 0004
+-------------+-------------+-------------+-------------+
bb+08 | Bus Error Register | 2008 0008
+-------------+-------------+-------------+-------------+
bb+0C | Error Interrupt Control | Error Vector | 2008 000C
+-------------+-------------+-------------+-------------+
bb+10 | Reserved | Interrupt Destination | 2008 0010
+-------------+-------------+-------------+-------------+
bb+14 |IP Interrupt Mask Register | Reserved | 2008 0014
+-------------+-------------+-------------+-------------+
bb+18 | Reserved | IP Interrupt Destination | 2008 0018
+-------------+-------------+-------------+-------------+
bb+1C | IP Interrupt Source | Reserved | 2008 001C
+-------------+-------------+-------------+-------------+
bb+20 | Starting Address | Unused | 2008 0020
+-------------+-------------+-------------+-------------+
bb+24 | Ending Address | Unused | 2008 0024
+-------------+-------------+-------------+-------------+
bb+28 | Unused | BCI Control Register | 2008 0028
+-------------+-------------+-------------+-------------+
bb+2C | Write Status Register | 2008 002C
+-------------+-------------+-------------+-------------+
bb+30 | | 2008 0030
to . Unused .
bb+3C | | 2008 003C
+-------------+-------------+-------------+-------------+
bb+40 | User Interrupt Control | Vector | 2008 0040
+-------------+-------------+-------------+-------------+
bb+44 | | 2008 0044
to . Unused .
bb+EC | | 2008 00EC
+-------------+-------------+-------------+-------------+
bb+F0 | General Purpose Register 0 | 2008 00F0
+-------------+-------------+-------------+-------------+
bb+F4 | General Purpose Register 1 | 2008 00F0
+-------------+-------------+-------------+-------------+
bb+F8 | General Purpose Register 2 | 2008 00F8
+-------------+-------------+-------------+-------------+
bb+FC | General Purpose Register 3 | 2008 00FC
+-------------+-------------+-------------+-------------+
FIGURE 12.1 BIIC INTERNAL REGISTERS
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12.3.2 DEVICE REGISTER (R/W,DMW,DCLOL) -
31 24 23 16 15 08 07 00
+--------------+--------------+--------------+--------------+
2008 0000| Revision Code | Device Type |
+--------------+--------------+--------------+--------------+
The Device type field is used to identify the type of BI Node. The
KA820'S device register has a 0105 in this 16 bit field. The revision
field is broken up as follows:
CPU Rev ------------------ bits <31:27>
microcode patch rev ------ bits <26:17>
secondary patches loaded-- bit <16>
12.3.3 BI CONTROL And STATUS REGISTER - This register is only written
by the KA820 microcode during initialization, to clear the BROKE bit
after a successful selftest. The operating system should set the Hard
and Soft Error Interrupt Enable bits during its initialization routine,
to enable error interrupts to be generated. It also has responsibility
for the Arb field, which is set to round robin mode at powerup by each
BIIC.
31 24 23 16 15 10 08 07 03 00
+---------------+---------------+-+-+-+-+-+-+-+-+-+-+---+-------+
bb+04| 0's | BIIC Type | | | | | | |0| | | |ARB|NODE ID|
+---------------+---------------+|+|+|+|+|+|+-+|+|+|+---+-------+
| | | | | | | | |
HES ---+ | | | | | | | |
SES -----+ | | | | | | |
INIT ------+ | | | | | |
BROKE -------+ | | | | |
STS -----------+ | | | |
SST -------------+ | | |
UWP -----------------+ | |
HEIE ------------------+ |
SEIE --------------------+
BIIC Type (RO)--This field indicates the type of BI interface chip that
is used. This field is Read-only and is always read as 000001 in this
implementation.
HES (RO)--Hard Error Summary. This bit indicates that one or more of
the hard error bits (except TDF) in the Bus Error Register are set.
SES (RO)--Soft Error Summary. This bit indicates that one or more of
the soft error bits in the Bus Error Register are set.
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INIT (W1C,DCLOS,STOPS)--INIT Bit. This bit is not used by the KA820.
BROKE (W1C,DCLOS)-- The BROKE bit indicates that the KA820 has not
successfully completed its self-test. This bit is cleared by microcode
when the self-test has been passed.
STS (R/W,DCLOC)-- The Self-Test Status bit indicates the result of the
BIIC's internal self-test. This bit is set to a '1' if the self-test
passes, and it directly enables the BIIC's BI drivers. Since this is a
normal R/W bit, it can be altered by a Write-command directed at this
register.
SST (SC)-- Start Self-Test. Writing a '1' to this bit location forces
the initiation of the BIIC Selftest, as well as assertion of BCI DCLO L
which initiates a selftest to the rest of the KA820. Reads to this bit
location always return a '0'. The STS bit is reset by the BIIC at the
same time the SST bit is set, in order to allow proper recording of the
self-test results.
| UWP (W1C,DCLOC,STOPC) -- The Unlock Write Pending bit is set when the
| KA820 issues a Read/Lock transaction, and it is cleared when the
| subsequent Write/Unlock is generated. Since a VAX instruction that
| causes microcode to generate a Read/Lock also generates a Write/Unlock,
| this bit should always be read as a 0 by instructions executed by the
| KA820, except if a machine check is generated that breaks up this
| sequence.
HEIE (R/W,DCLOC,STOPC)--The Hard Error Interrupt Enable bit is normally
set by the operating system software so that an error interrupt is
generated when HES is asserted.
SEIE (R/W,DCLOC,STOPC)--The Soft Error Interrupt Enable bit is set by
the operating system software to allow an error interrupt to be
generated when SES is asserted.
ARB (R/W,DCLOC)--The two Arbitration Control Bits determine the mode of
arbitration to be used by the KA820 as follows:
ARB
1 0 Meaning
--- -----------------------------
0 0 Round Robin Arbitration
0 1 Fixed High Priority
1 0 Fixed Low Priority
1 1 Disable Arbitration (see explanation below)
These bits are controlled by operating system software, and are
normally written to 0's.
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NODE ID (RO,DMW,DCLOL)-- This field is Read-only and indicates the Node
ID assigned to this Node. This information is loaded from the BCI
I<3:0> H lines during the last cycle in which BCI DC LO L is asserted,
and it reflects the encoded node ID plug that is plugged onto this slot
of the BI backplane.
Node 2 is the normal node ID assigned to the Scorpio primary
processor, according to DEC convention.
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12.3.4 BUS ERROR REGISTER (W1C,DCLOC) - This register, as weel as the
equivalent register of other BI nodes can be read by software following
a BI error to determine the cause of the error. Any time that an error
interrupt is generated, the BIIC that generated the error sets the
appropriate bit in its Bus Error register.
In order for each BIIC to generate these interrupts, the operating
system should set the hard and soft error interrupt enable bits of each
BI node in the system. This is done by writing to the BICSR of each
node, as was described in the description of that register.
The operating system has the responsibility of clearing the error bits
in the BER after reading the register. The procedure required is to
re-read the BER after clearing the appropriate bit to assure that
another wasn't set in the meantime. Alternatively it can read the hard
and soft error summary bits in the appropriate BI CSR to determine if
another error bit has been set.
During initialization the operating system can write 3FFF 0007 to the
BERs of each BIIC to clear all error bits.
31 24 23 16 15 08 07 03 00
+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+---------------+-------+-+-+-+-+
bb+08|0| | | | | | | | | | | | | | | | 0's | | | | | |
+-+-+|+|+|+|+|+|+|+|+|+|+|+|+|+|+---------------+-------+|+|+|+|+
| | | | | | | | | | | | | | | | | | |
NMR-+ | | | | | | | | | | | | | | | | | |
MTCE--+ | | | | | | | | | | | | | | | | |
CTE ----+ | | | | | | | | | | | | | | | |
MPE ------+ | | | | | | | | | | | UPEN ----+ | | |
ISE --------+ | | | | | | | | | | IPE -------+ | |
TDF ----------+ | | | | | | | | | CRD ---------+ |
IVE ------------+ | | | | | | | | NPE -----------+
CPE --------------+ | | | | | | |
SPE ----------------+ | | | | | |
RDS ------------------+ | | | | |
RTO --------------------+ | | | |
STO ----------------------+ | | |
BTO ------------------------+ | |
NEX --------------------------+ |
ICE ----------------------------+
SOFT ERROR BITS
|<------ HARD ERROR BITS ------>| |<--->|
<31:16> <2:0>
NOTE
Unless otherwise noted all BER Bits can be set during BI
Transactions (meaning transactions from the BIIC that actually
are transmitted on the BI Bus) as well as Loopback Requests
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BI PROGRAMMING 24 Jan 86
(which do not actually go out on the BI but instead are
"looped-back" internally to the BIIC).
HARD ERROR BITS
---- ----- ----
NMR (W1C,DCLOC)-- NO ACK to multi-responder command received. This bit
is set if a NO ACK command confirmation is received for an INVAL, STOP,
INTR, or IPINTR command.
MTCE (W1C,DCLOC)--Master Transmit Check Error. During cycles of a
transaction in which the KA820 is the only source of data on the BI D,
I and P lines, the BIIC verifies that the transmitted data matches the
received data from the BI, or else this bit is set. This check is not
performed on the assertion of its encoded ID on the I lines, during the
Imbedded ARB Cycle.
CTE (W1C,DCLOC)--Control Transmit Error. This bit is set when there is
an assertion of the NO ARB, BSY, or the CNF<2:0> Control Lines, and the
BIIC detects the deasserted state.
MPE (W1C,DCLOC)--Master Parity Error. This bit is set during a master
transaction if a parity error is detected on the bus during a data
cycle of a transaction that has an ACK confirmation on the CNF<2:0>
lines.
| ISE (W1C,DCLOC)--Interlock Sequence Error. This bit is set if the
| KA820 attempts to generate a Write/Unlock transaction without having
| done a prior Read/Lock transaction.
TDF (W1C,DCLOC)--Transmitter during fault. This bit is set if the BIIC
was driving the BI D and I Lines (or only the I Lines during the
Imbedded ARB Cycle) during a cycle that resulted in a parity error.
This bit is also set during slave transactions if the BIIC detects a
parity error on Read Data that it transmits. Diagnostic Software that
reads this register should interpret a set TDF without a set MPE, CPE,
or IPE as an indication that the BIIC detected a parity error on its
own transmitted Read Data.
IVE (W1C,DCLOC)--IDENT vector error. This bit is set by the BIIC if
anything but an ACK confirmation is received from an IDENTing Master
after an Interrupt Vector has been sent out. This would only occur
when the KA820 is used as an I/O controller, such that it generated an
interrupt.
CPE (W1C,DCLOC)--Command Parity Error. This bit is set when the BIIC
detects a parity error during a command/address cycle. This can be
from a BI Transaction or a Loopback Request C/A Cycle.
SPE (W1C,DCLOC)--Slave Parity Error. This bit is set by the BIIC when
it detects a parity error during the Data Cycle of a Write transaction
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BI PROGRAMMING 24 Jan 86
directed at the KA820's RXCD or BIIC registers.
RDS (W1C,DCLOC)--Read Data Substitute. This bit is set if a Read Data
Substitute or RESERVED Status Code is received during a Read-type or
IDENT (for Vector status) transaction. The BIIC logic also requires a
successful parity check for the data cycle that contains the RDS Code,
in order for this bit to be set. This bit gets set even if the
transaction is aborted some time after the receipt of the RDS or
RESERVED Code.
RTO (W1C,DCLOC)--Retry Timeout. This bit is set if the KA820 receives
4096 consecutive RETRY responses from the Selected Slave for the same
transaction.
STO (W1C,DCLOC)--Stall Timeout. This bit is normally set by the BIIC
if STALL is asserted on the RS<1:0> Lines for 128 consecutive cycles,
but the PCntl never asserts the STALL code on these lines.
BTO (W1C,DCLOC)--Bus Timeout. This bit is set if the BIIC is unable to
start at least one pending transaction (out of possibly several that
are pending) before 4096 cycles have elapsed.
NEX (W1C,DCLOC)--Non-Existent Address. This bit is set when a NOACK
response is received for a Read-type or Write-type command sent by the
BIIC. Note that this bit is set only if the Master Transmit Check of
the Command/Address cycle was successful and that this bit is not set
for NOACK responses to other commands.
ICE (W1C,DCLOC)--Illegal Confirmation Error. A reserved or illegal
CNF<2:0> code has been received during a transaction. This bit can be
set during either Master or Slave transactions. Note that NO ACK is
not considered an Illegal response for Command Confirmation.
PARITY MODE
------ ----
UPEN (RO)--User Parity Enabled. This is a Read-Only Bit that indicates
the BIIC Parity Mode. It should always be read a '0' indicating that
the BIIC provides the Parity Generation, rather than the PCntl.
SOFT ERROR BITS
---- ----- ----
IPE (W1C,DCLOC)--ID Parity Error. A parity error is detected on the
encoded ID that is asserted when the KA820 is the current BI master,
during an Imbedded ARB cycle. This also sets the TDF Bit.
CRD (W1C,DCLOC)--Corrected Read Data. A corrected read data status
code was received from BI memory during a Read transaction. This bit
gets set even if the transaction aborts after the CRD Status Code has
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BI PROGRAMMING 24 Jan 86
been received.
NPE (W1C,DCLOC)--Null Bus Parity Error. Odd parity was detected on the
bus during the second cycle of a two-cycle sequence during which NOARB
and BUSY were unasserted.
12.3.5 ERROR INTERRUPT CONTROL REGISTER - This register is programmed
for controlling error interrupts that are generated by the KA820's
BIIC.
31 24 23 19 16 15 13 08 07 02 00
+-------------+-+-+-+-+-+-------+---+-----------+-----------+---+
bb+0C| 0's | | |0| | | LEVEL |0 0| Vector |0 0|
+-------------+|+|+-+|+|+-------+---+-----------------------+---+
| | | |
INTAB ---+ | | |
INTC ------+ | |
SENT ----------+ |
FORCE -----------+
The Error Interrupt Control Register controls the operation of
interrupts initiated by a BIIC detected BUS error (which sets a bit in
the Bus Error Register) or by the setting of a FORCE bit in this
register. In the description that follows an error interrupt request
is the "OR" of the FORCE Bit and all Bus Error Register Bits (assuming
the error interrupt enables are set in the BI Control and Status
Register).
INTAB (W1C,DCLOC,SC)-- The Interrupt Abort bit is set if an INTR
command, sent under the control of this register, is aborted (i.e. a
NOACK or illegal confirmation code is received). INTAB is a status bit
that is set by the BIIC and can only be reset by the User. It has no
effect on the ability of the BIIC to send or respond to further INTR or
IDENT transactions.
INTC (W1C,DCLOC,SC)--The Interrupt Complete bit is set when the vector
for an error interrupt has been successfully transmitted, or if an INTR
command sent under the control of this register has aborted. Removal
of the error interrupt request automatically resets this bit. No
interrupts are generated by this register when the INTC bit is set.
SENT (W1C,DCLOC,STOPC,SC)--The SENT bit indicates that an INTR command
for this interrupt has been sent, and that an IDENT command is
expected. This bit is cleared during an IDENT command following the
detection of a Level and Master ID match. This allows the interrupt to
be re-sent if this Node loses the INTR ARB, or if it wins but the
vector transmission fails.
Note also that de-assertion of the error interrupt request causes the
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 110
BI PROGRAMMING 24 Jan 86
SENT bit to be cleared.
FORCE (R/W,DCLOC,STOPC)-- When set, this bit forces an error interrupt
request in the same way that a bit getting set in the Bus Error
Register does.
LEVEL (R/W,DCLOC)--The LEVEL field determines the level(s) at which
INTR commands are transmitted under the control of this register.
Normally only one of the 4 level bits is set.
The LEVEL field also helps determine whether this control register will
respond to IDENT commands. If any level bits of the received IDENT
command match the LEVEL field in this register, then this register will
arbitrate for the IDENT, assuming that there is also a match in the
destination mask.
This functionality makes it possible to operate IDENT commands either
to match the LEVEL exactly, or to match levels on a
"greater-than-or-equal" basis.
Note that the BIIC does not transmit an Error Interrupt if none of the
LEVEL Bits are set.
VECTOR (R/W, DCLOC)-- The Vector field contains the vector used during
error interrupt sequences. It is transmitted when this Node wins an
IDENT ARB cycle on an IDENT transaction that matches the conditions in
the Error Interrupt Control Register.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 111
BI PROGRAMMING 24 Jan 86
12.3.6 BCI CONTROL REGISTER -
31 24 23 18 17 15 13 11 9 8 7 6 5 4 0
+---------------+-----------+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-----+
bb+28| 0's 0's | | | | | | | | | | | | | | | | 0's |
+---------------+-----------+|+|+|+|+|+|+|+|+|+|+|+|+|+|+|+-----+
| | | | | | | | | | | | | | |
BURSTEN ----------+ | | | | | | | | | | | | | |
IPINTR/STOP FORCE---+ | | | | | | | | | | | | |
MSEN -----------------+ | | | | | | | | | | | |
BDCSTEN ----------------+ | | | | | | | | | | |
STOPEN -------------------+ | | | | | | | | | |
RESEN ----------------------+ | | | | | | | | |
IDENTEN ----------------------+ | | | | | | | |
INVALEN ------------------------+ | | | | | | |
WINVALEN -------------------------+ | | | | | |
UCSREN -----------------------------+ | | | | |
BICSREN ------------------------------+ | | | |
INTREN ---------------------------------+ | | |
IPINTREN ---------------------------------+ | |
PNXTEN -------------------------------------+ |
RTOEVEN --------------------------------------+
|
|
| NOTE
|
| Following the successful completion of selftest, this register
| contains 0000 0710. When VAX code is ready to accept
| interrupts and IP Interrupts, a value of 0000 0770 should be
| written to this register by software.
Following the Bit name in the following Bit Descriptions are the Bit
Characteristics (as described at the beginning of the Register Section)
and to the right of the dash(-) are a set of further designations for
the BCICSR Bits, that describe the effect of the Enable Bit on BIIC
Operation. These designations are defined as follows:
o DS: Disables Selection. When a bit of this type is reset, the
BIIC suppresses the appropriate SEL/SC Assertion and also doesn't
respond in any way to transactions corresponding to that Enable
Bit. For instance, if the INTREN Bit is reset, then the BIIC won't
be selected for any INTR Transactions that are received from the
BI. Most of the Enable Bits are in this class.
o SC: Special Case. This covers the special cases that do not
simply disable participation. See the specific Bit description for
details on how the Bit actually operates.
o NA: Not Applicable. This category includes all bits within this
register that have no effect on Slave selection.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 112
BI PROGRAMMING 24 Jan 86
BURSTEN (R/W,DCLOC - NA)-- BURST Enable. When set, this bit causes BI
NO ARB L to be asserted continuously after the next successful arb
until the BURSTEN bit is reset or BCI MAB L is asserted.
|
|
| NOTE
|
| Burst mode is not used by microcode and it is not recommended
| that VAX code ever set this bit.
|
|
| IPINTR/STOP FORCE (R/W,DCLOC - NA)-- IP Interrupt or Stop Force bit.
| This bit is used by microcode during an MTPR to the IPIR or BISTOP
| register. It causes the BIIC to arbitrate for the bus and transmit an
| IP INTR command, depending upon which IPR is written. Microcode writes
| the appropriate command to the Force Bit IPINTR/STOP Command register,
| the destination to the Destination register, and then sets this bit in
| the BCI Control register to initiate an IPINTR or a BI STOP command.
|
| Software can generate an IPINTR or BI STOP by simply doing a write of
| the targetted node(s) to either the IPIR or BI STOP processor
| registers.
MSEN (R/W,DCLOC - DS)-- Multicast Space Enable. When set, this bit
causes the BIIC to assert SEL and the appropriate SC<2:0> code
following the receipt of a Read-type or Write-type command directed at
"Broadcast Space" (as defined in the BI Spec). This bit is normally
left cleared so that the KA820 doesn't respond to multicast space
commands.
BDCSTEN (R/W,DCLOC - DS)-- BROADCAST Enable. When set, this bit causes
the BIIC to assert SEL and the appropriate SC<2:0> code following the
receipt of a BROADCAST command. This bit is normally left cleared so
that the KA820 doesn't respond to broadcast commands.
STOPEN (R/W,DCLOC - DS)-- STOP Enable. When set, this bit causes the
BIIC to assert SEL and the appropriate SC<2:0> code following the
| receipt of a STOP command. This bit should be left cleared because the
| KA820 doesn't respond to the STOP command.
RESEN (R/W,DCLOC - SC)-- Reserved Enable. When set, this bit causes
the BIIC to assert SEL and the appropriate SC<2:0> code following the
receipt of a reserved command code (see RESERVED COMMANDS in the BIIC
Transaction Operation Section).
IDENTEN (R/W,DCLOC - SC)-- IDENT Enable. When set, this bit causes the
BIIC to assert SEL and the appropriate SC<2:0> code following the
receipt of an IDENT command. This bit affects only the output of SEL
and the IDENT SC code. Therefore, the BIIC always participates in
IDENT Transactions that select this Node even if this enable bit is
reset.
INVALEN (R/W,DCLOC - DS)-- INVAL Enable. When set, this bit causes the
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 113
BI PROGRAMMING 24 Jan 86
BIIC to assert SEL and the appropriate SC<2:0> code following the
receipt of an INVAL command. This bit is set by initialization
microcode to enable BI invalidates to get forwarded by the PCntl to the
Mchip's cache tag array.
WINVALEN (R/W,DCLOC - SC)-- Write Invalidate Enable. When set, this
bit causes the BIIC to assert SEL and the appropriate SC<2:0> code
following the receipt of a Write-type command whose address has D<29> =
0 (i.e. not I/O space). This bit is set by initialization microcode
to enable the BIIC to forward BI write addresses to the PCntl, so that
it in turn can send invalidate requests to the Mchip's cache tag array.
UCSREN (R/W,DCLOC - DS)-- User CSR Space Enable. When set, this bit
causes the BIIC to assert SEL and the appropriate SC<2:0> code
following the receipt of Read-type or Write-type command directed at
this node's User CSR Space. This bit is set by initialization
microcode to enable access to the KA820's User CSR address space.
BICSREN (R/W,DCLOC - SC)-- BIIC CSR Space Enable. When set, this bit
causes the BIIC to assert SEL and the appropriate SC<2:0> code
| following the receipt of a Read-type or Write-type command to its BIIC
| CSR Space. This bit is not set by initialization microcode, and there
| should be no reason for software to set it.
INTREN (R/W,DCLOC - DS)-- INTR Enable. When set, this bit causes the
BIIC to assert SEL and the appropriate SC<2:0> code following the
| receipt of an INTR command. This bit would normally be set by the
| operating system software, since initialization microcode leaves it in
| the cleared state.
IPINTREN (R/W,DCLOC - SC)-- IP INTR Enable. When set, this bit causes
the BIIC to assert SEL and the appropriate SC<2:0> code following the
receipt of an IP INTR command that matches the IP Interrupt Mask
Register. This bit only enables the IPINTR SEL/SC Code, and selection
by IP INTR commands directed at this Node is unaffected by the state of
| this enable. This bit would normally be set by the operating system
| software, since initialization microcode leaves it in the cleared
| state.
In order to disable selection for all IP INTR Commands at this Node the
operating system software should clear the IP INTR MASK Register. This
assures that no IP INTR Commands can select this Node.
PNXTEN (R/W,DCLOC - NA)-- Pipeline NXT Enable. When set, this bit
causes the BIIC to provide an extra BCI NXT L cycle (i.e one more than
the number of longwords transferred) during WRITE Transactions. This
extra BCI NXT L cycle occurs after the last NXT L cycle for Write data,
and is used to increment the Write-SILO address counter to the address
of the C/A data for the next transaction. This bit is set by
initialization microcode, along with the pipeline enable bit in the
PCntl CSR, to enable pipeline mode for memory write transactions.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 114
PROGRAMMING THE WATCH CHIP 24 Jan 86
13.0 PROGRAMMING THE WATCH CHIP
The battery backed up watch chip is used to keep time of year information
when the Scorpio system is powered off. Its battery is spec'd to keep it
running for 100 hours without the system being powered on. System software
then reads this time after each powerup, and uses it to load the Time of
Day Register (TODR) in the Mchip at IPR 1B. The watch chip is accessed by
software with I/O addresses.
I/O addresses 200B 8000 through 200B 801A are used to read the contents of
the watch chip each time the CPU is powered on. Since the watch chip
provides time in terms of months, hours, etc, instead of a 32 bit count,
the operating system must make a conversion to the correct 32 bit count to
load into the TODR clock register within the Mchip.
In order to read the watch chip internal registers, about 600 ns is
required by the hardware for each read, best case. In the event the NI
LANCE chip is simultaneously using the PCI bus, and a packet is being
received, up to 4.8 microseconds could be required to read one byte of
data, worst case. This, coupled with execution time of the instruction
implies that reading one register of the watch chip will require from 2 to
6 usec. Five registers within the watch chip must be read, along with two
CSR registers to get the complete time of the year, so 14 to 42 usecs could
be required to obtain all the data to set the TODR in the Mchip. (If an
update is in progress within the chip, up to another 2 msec could be
required).
The chip consists of 64 eight bit registers, 10 of which contain time of
day data, 4 of which are CSRs, and the remaining 50 provide 50 bytes of
battery backed-up RAM locations. They are addressed as follows:
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 115
PROGRAMMING THE WATCH CHIP 24 Jan 86
Address Function Comments
200B 8000 seconds
200B 8002 second alarm not used
200B 8004 minutes
200B 8006 minute alarm not used
200B 8008 hours
200B 800A hour alarm not used
200B 800C day of week not used
200B 800E date of month
200B 8010 month
200B 8012 year
200B 8014 CSR A BUSY bit
200B 8016 CSR B OFF (start and stop) bit
200B 8018 CSR C not used
200B 801A CSR D VALID (valid time) bit
200B 801C 1st byte of RAM not currently used
. . .
. . .
200B 807E 50th byte of RAM .
The following shows an example of what is read from the chip and how it's
interpreted.
ADDRESS UNITS DECIMAL HEX RANGE HEX RANGE
RANGE (at chip) (at CP DAL)
200B 8000 seconds 0 - 59 00 - 3B 00 - 76
200B 8004 minutes 0 - 59 00 - 3B 00 - 76
200B 8008 hours 0 - 23 00 - 17 00 - 2E
200B 800E day of mo. 1 - 31 01 - 1F 02 - 3E
200B 8010 month 1 - 12 01 - 0C 02 - 18
| 200B 8012 year 0 - 99 00 - 63 00 - C6
AN EXAMPLE SHOWING DATA AS READ FROM THE CHIP AND AS IT APPEARS DUE TO
BIT 7 BEING READ AS BIT 0:
CHIP OUTPUT DATA AS READ BY SOFTWARE
binary byte hex DAL byte 0 hex
21 seconds [0001 0101] 15 [0010 1010] 2A
58 minutes [0011 1010] 3A [0111 0100] 74
5:00 hours [0000 0101] 05 [0000 1010] 0A
15th date [0000 1111] 0F [0001 1110] 1E
Feb month [0000 0010] 02 [0000 0100] 04
* undefined data
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 116
PROGRAMMING THE WATCH CHIP 24 Jan 86
13.1 CSR DEFINITIONS
The following CSR definitions have bit 7 moved to bit position 0, and the
rest of the bits shifted to the right one position to reflect the way
they'll be read from the CP DAL by the I/Echip. Software should read or
write this register with a MOVB or MOVW instruction to assure that the data
is in byte 0.
CSR A: I/O Address 200B 8014
15 8 7 6 5 1 0
+--------------------------------+-----+-----+-------------------+-----+
| UNDEFINED | MBZ | 1 | MBZ | BUSY|
+--------------------------------+-----+-----+-------------------+-----+
Bits <15:8> Not used, and if read are undefined.
Bits <7:1> (Miscellaneous setup bits)
|
|
| NOTE
|
| These bits must always be written as shown
| whenever the chip is initialized or the time
| is changed. Failure to do so will result in
| the watch chip to not keep accurate time.
|
|
Read/Write bits by software, that must be written as shown when setting
the time in the watch chip.
These bits are not changed by the chip, and are not affected by the
chip going into or out of battery backup mode, as long as the battery
voltage remains within spec. (This is determined by reading the Valid
Time bit at I/O address 200B 801A.
Bit <0> BUSY
Read only bit that is read by software prior to accessing the time
registers. This bit must be = 0 in order to read the time.
1 = Chip busy, time registers undefined.
0 = Chip not busy, OK to read the time registers.
If BUSY = 1: The maximum time required for the internal update is
about 2 ms. Software can either time out, or continue reading this bit
until it is read as a 0.
If BUSY = 0: there are a minimum of 244 usec available prior to the
next update cycle. (To completely read the 5 time registers should
require about 40 Usec, worst case).
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 117
PROGRAMMING THE WATCH CHIP 24 Jan 86
The update to the time registers occurs once per second. (Statistically
this will occur once per 500 attempts to read the watch chip).
CSR B: I/O Address 200B 8016
15 8 7 4 3 2 1 0
+----------------------------------+-----------+-----+-----+-----+-----+
| UNDEFINED | MBZ | 1 | 1 | MBZ | OFF |
+----------------------------------+-----------+-----+-----+-----+-----+
Bits <15:8> Not used, and if read are undefined.
Bits <7:1> (Miscellaneous setup bits)
|
|
| NOTE
|
| These bits must always be written as shown whenever the chip is
| initialized or the time is changed. Failure to do so will
| result in the watch chip to not keep accurate time.
|
|
Must be written as shown above by software, anytime there's a powerup
from a condition where the BBU failed. This would probably be part of
the routine for setting the time into the chip, since that is done each
time the BBU fails, or goes out of spec.
This register is not affected by the chip going into or out of the
normal BBU mode, where the battery voltage remains within spec.
Bit <0> OFF (used to turn chip on and off when setting the time)
Read/write bit.
Written with a 1 to stop the watch chip, so that software may load the
time registers. This bit must be set prior to setting the time. If
the chip is in the middle of an update, setting this bit aborts the
update.
Written with a 0 to start the watch chip after setting the time
registers. The internal time then starts to update every second.
CSR C: I/O Address 200B 8018 This interrupt status register is read only,
and if read is undefined. It is not used, since the interrupt
functionality of the watch chip isn't used on the KA810.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 118
PROGRAMMING THE WATCH CHIP 24 Jan 86
CSR D: I/O Address 200B 801A
15 8 7 1 0
+---------------------------------+------------------------------+-----+
| UNDEFINED | Read as zeros |VALID|
+---------------------------------+------------------------------+-----+
This register is read only, and is read by the macrocode, before reading
the time registers, to verify the validity of the time.
Bits <15:8> Not used, and if read are undefined.
Bits <7:1> Read as 0's and not used.
Bit <0> VALID time
Read only bit, that is set to 1 when read by software.
VALID = 1; the time represented in the chip's registers is valid.
VALID = 0; indicates that the battery voltage went below spec during
the BBU mode when AC power to the system was turned off.
If the battery backup voltage goes out of spec, this bit is set to 0 by
the battery backup sensing circuitry during powerup to indicate that
the time registers are undefined.
This bit is automatically set to a 1 when this register is read. After
reading this bit as a 0, the invalid time registers must be updated
immediately. Since this bit was just set to a 1 by the read, it can no
longer be used to indicate that the chip contains a valid time setting.
13.2 OPERATING SYSTEM SOFTWARE
The operating system software can run into two different conditions at
powerup time. They are when the battery backup has stayed within spec,
and when it has gone out of spec. The latter can occur due to the
battery being removed, or the battery voltage dropping below its spec'd
value, when power was removed from the system. The following two
sections describe what the operating system powerup software must do.
13.2.1 NORMAL POWERUP, VALID BBU - The sequence of events for the
powerup software is to first read the BUSY bit in CSR A, to assure that
an update isn't in progress. If this bit is read as a 1 the watch chip
is doing an update, and the data is invalid until it is through. In
this case the software must try at a later time to access this CSR.
The maximum time for the update is 1984 usec, assuming that it just
started. If this bit is read as a 0, then the chip's time/date
registers can be read and used by the software.
KA820-AA SPEC - PART II - USER AND PROGRAMMING INFORMATION Page 119
PROGRAMMING THE WATCH CHIP 24 Jan 86
The first thing that the software does, before reading the 5 time/date
registers, is to read the VALID bit in CSR D, to assure that the time
data within them is accurate. Since this bit gets set to 1 by the chip
upon being read, it can only be read once. If this bit is read as 1
the software reads the 5 registers and converts the data into a 32 bit
count. It then loads this count into the TODR register.
13.2.2 POWERUP - BBU FAILURE - If the VALID bit is read as a 0, the
software must prompt for the time and date from the operator, convert
it to the proper binary format for the TODR register in the Mchip, and
then load it, using the TODR IPR. It must also convert the time and
date to the proper binary format for each of the 5 time registers
within the watch chip. It then loads each of them with the correct
count as follows.
Before writing to the watch chip, the OFF bit in CSR B must be written
with a 1 to stop the chip. Even if the chip is in the middle of an
update, setting this bit will abort the rest of the cycle so that the
| new time can be entered. At this time CSR A and B must also be
| initialized with the data as shown above. Following the loading of the
5 bytes of data and the 3 CSR registers, the OFF bit in CSR B is
written with a zero, which turns on the watch chip to start updating
the time. When writing this bit, bits <7:0> must also be written as
shown above.
-------------- next part --------------
EK-KA825-MA-001
KA825 Maintenance Advisory
(FOR INTERNAL USE ONLY)
MARCH, 1987
1.0 Purpose of Document
This document provides a general description of the VAX 8250/8350
systems by stating only the differences from the VAX 8200/8300 systems.
It is intended as a guide to assist VAX 8200/8300 trained field service
engineers in the maintenance of the VAX 8250/8350 systems.
2.0 Product Description
2.1 VAX 8200/8300 and VAX 8250/8350 Differences Overview
The VAX 8250 and 8350 systems are enhanced systems giving around 20%
greater performance than the standard 8200/8300 systems. This has
been accomplished by installing a faster CPU module, the KA825, in
place of the KA820. This new module is a T1001-YA and is a faster
version of the T1001-00 module currently used for the KA820. Both
modules physically look the same, except that the T1001-YA contains
faster components and a faster clock crystal ( see Table 1 below ).
Architecturally, the KA820 and KA825 are identical. All registers
and console commands are identical for the KA825 as well. The
differentiating factor between the two CPUs is bit 23 of the SID
register (most significant bit in the major revision field) which is
set for a KA825.
2.2 CPU Differences
The differences between the KA820 and KA825 CPU module are
summarized in Table 1 below.
Table 1
-------
Elements | KA825 | KA820
----------------------------------------------------------------
CPU Module | T1001-YA | T1001-00
----------------------------------------------------------------
BI Clock | 200 nanoseconds | 200 nanoseconds
----------------------------------------------------------------
CPU Clock | 160 nanoseconds | 200 nanoseconds
----------------------------------------------------------------
Xtal | 50 MHz | 40 MHz
----------------------------------------------------------------
Cache/TB RAMs | 35 nanoseconds | 45 nanoseconds
----------------------------------------------------------------
V11 chip set | 160ns parts | 200ns parts
----------------------------------------------------------------
DC346 | date code 8644 min | all date codes
----------------------------------------------------------------
DC347 | date code 8649 min | all date codes
----------------------------------------------------------------
DC348 | date code 8644 min | all date codes
----------------------------------------------------------------
3.0 OPERATING SYSTEMS
3.1 VMS
The first version of VMS that will officially support the KA825
is version 4.5. However, the error logger in this version of VMS
will report the KA825 as a KA820. This will be fixed in version
4.6 of VMS.
3.2 ULTRIX-32
The first version of ULTRIX that will officially support the KA825
is version 2.0.
4.0 DIAGNOSTICS
Changes have been made to both the Diagnostic Supervisor, (EBSAA)
and the EEPROM Utility, (EBUCA) to support the KA825 CPU. These two
programs should be available in diagnostic release 28.
Until this happens, a utility program floppy disk containing both
the correct Diagnostic Supervisor, and EEPROM Utility program will
be found in the loose parts bag that ships with the 8250 and 8350
systems. Replace the Utility Program floppy in the Owner's Manual,
found in the software box, with this new floppy. Copy this new
Diagnostic Supervisor from the utility floppy into your diagnostic
account for use when running diagnostics on the system.
Also the Diagnostic Supervisor that is on the floppy marked "VAX
8200 Diag Super + Auto" needs to be updated. To do this delete the
old Diagnostic Supervisor "EBSAA.EXE" on the "VAX 8200 Diag Super +
Auto" floppy, and copy the new one from the utility floppy. Writeboot
will have to be run on this disk again to allow the Diagnostic
Supervisor to be booted. Invoke the Writeboot program by typing,
MC Writeboot. Then answer the target file question with the drive the
floppy is in, account and program name. As shown:
EX: CSA2:[sysmaint]EBSAA.EXE
The next question will be logical block number, which should be
answered 2. The last is starting address which should be answered,
10000.
The new revisions are as follows:
EBSAA Rev 10.6 min
EBUCA Rev 2.3 min
4.1 EBSAA
The changes made to the Diagnostic Supervisor are to the software
timing loop to compensate for the faster CPU speed.
NOTE
----
The human interface section of the Diagnostic
Supervisor has NOT been modified in this release
to understand KA825 as a legal CPU type. Therefore,
it must be attached as a KA820.
4.2 EBUCA
The EEPROM Utility program has been modified in this release
to understand the difference between KA820 and KA825 CPUs, and
report them appropriately.
Since it is the most significant bit (23) of the CPU revision
field in the SID register that determines the type of CPU, the CPU
revision will always be the decimal equivalent of the CPU revision
plus 16.
Table 2
KA825 at CPU revision A1
SID Bit Positions | 23 | 22 | 21 | 20 | 19 |
--------------------------------------------------
Register contents | 1 | 0 | 0 | 0 | 1 |
--------------------------------------------------
Bit weights | 16 | 8 | 4 | 2 | 1 |
--------------------------------------------------
Decimal value | 16 | 0 | 0 | 0 | 1 |
--------------------------------------------------
CPU rev field = 16 + 1 or 17
4.3 EBKAX
EBKAX version 1.5 will get a "Hard error while testing KA0. More
than one RX50 interrupt received." error in test 39 when run on
a KA825 CPU. This is caused by the speed increase of the KA825 CPU
coupled with the algorithm the diagnostic uses to service interrupts.
For the present time it is recommended that EBKAX version 1.3 be
used in place on EBKAX version 1.5. Version 1.3 does not contain
the tests that check the RX50 therefore this version will not see
the problem. EBKAX version 1.3 was distributed in prerelease B for
the KA820, kit part number; PR-FG87B-DE.
5.0 MICROCODE
The KA825 will ship with microcode revision 23.
6.0 MAINTENANCE
The VAX 8250/8350 system maintenance strategy is the same as
that established for the VAX 8200/8300 systems. All procedures
currently used for VAX 8200/8300 systems should be followed for
the VAX 8250/8350 systems.
7.0 SITE PREPARATION
The same site preparation procedures and considerations that were
established for the VAX 8200/8300 systems apply to the VAX 8250/8350
systems. These consist of site layout, electrical, and environmental
requirements.
8.0 INSTALLATION
If there is a KDB50 installed in the system, be sure it has a pass 5
BIIC. If it doesn't, you will see a memory illegal confirmation error
on booting the system. A pass 5 BIIC can be identified by the part
number, which is stamped in one of the corners of the BIIC chip. A
pass 4 has a part number of 324D; a pass 5 will be 324E. Otherwise,
the VAX 8250/8350 installation procedures will follow the same
procedures as those established for the VAX 8200/8300 systems.
9.0 CD KIT
There will be a new CD Kit generated that will contain the T1001-YA
module. The part number for this kit is A2-W1228-10.
10.0 DOCUMENTATION
Title Document Number
---------------------------------------------------
VAX 8200 Owner's Manual AZ-GN4AA-TE
VAX 8200 Installation Guide AZ-GN5AA-TE
VAX 8200 Minireference Manual AZ-GN6AA-TE
KA820 Processor Technical Manual EK-KA820-TM
VAX 8200 Field Maint. Printset MP01786-01
This current set of documentation for the 8200/8300 systems will
be updated to include the 8250/8350 systems. This updated documentation
should be available during Q1 of FY'88.
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