[Simh] Issues with VH simulation and 4.3BSD-Quasijarus

Cory Smelosky b4 at gewt.net
Wed Mar 8 23:49:57 EST 2017


All,

Seems 4.3BSD isn't seeing a DH-11 at all:

4.3 BSD Quasijarus UNIX #0: Sun Mar  7 12:42:05 PST 2004
    root at ucbvax:/usr/src/sys/GENERIC
real mem  = 67108864
SYSPTSIZE limits number of buffers to 18
avail mem = 65271808
using 18 buffers containing 147456 bytes of memory
VAX 11/780, serial# 1234(0), hardware ECO level 7(112)
mcr0 (el) at tr1
mcr1 (el) at tr2
uba0 at tr3
tmscp0 at uba0 csr 174500 vec 774, ipl 15
tms0 at tmscp0 slave 0
tms1 at tmscp0 slave 1
uda0 at uba0 csr 172150 vec 770, ipl 15
uda0: version 3 model 6
uda0: DMA burst size set to 4
ra0 at uda0 slave 0: ra92, size = 2940951 sectors
Changing root device to ra0a

SHOW CONFIGURATION:
VAX 11/780 simulator configuration

CPU     idle=VMS, idle enabled, model=VAX 11/780
       	64MB, HALT to SIMH
TLB     2 units
  TLB0    8192W
  TLB1    8192W
SBI
MCTL0   nexus=1, address=20002000
MCTL1   nexus=2, address=20004000
UBA     nexus=3, address=20006000, autoconfiguration enabled
MBA0    disabled
MBA1    disabled
TODR
       	12B
TMR
TTI
       	7b
TTO
       	7b
CS
       	256KB, not attached, write enabled
TC      disabled
TDC     disabled
DZ      disabled
VH      address=2013E120-2013E15F*, vector=C0-DC*, BR4, lines=64, 4
units
  VH0     attached to 8070, DHU mode, Modem
       	0 current connections
  VH1     DHU mode
  VH2     DHU mode
  VH3     DHU mode
CR      disabled
LPT     disabled
RP      disabled
RL      disabled
HK      disabled
RK      disabled
RQ      address=2013F468-2013F46B, vector=1F8*, BR5, UDA50, 4 units
  RQ0     1505MB, attached to ucbvax-ra92-root.dsk, write enabled
       	RD54, autosize, SIMH format
RQB     disabled
RQC     disabled
RQD     disabled
RY      address=2013FE78-2013FE7B, vector=B4, BR5, 2 units
  RY0     512KB, not attached, write enabled
       	double density
  RY1     512KB, not attached, write enabled
       	double density
TU      disabled
TS      disabled
TQ      TU81 (180MB), address=2013F940-2013F943, vector=1FC*, BR5, 4
units
  TQ0     not attached, write enabled, SIMH format
       	capacity=188MB
  TQ1     not attached, write enabled, SIMH format
       	capacity=188MB
  TQ2     not attached, write enabled, SIMH format
       	capacity=188MB
  TQ3     not attached, write enabled, SIMH format
       	capacity=188MB
XU      disabled
XUB     disabled
DMC     disabled

VAX 11/780 simulator V4.0-0 Beta
       	Simulator Framework Capabilities:
       		64b data
       		64b addresses
       		Threaded Ethernet Packet transports:PCAP:TAP:NAT:UDP
       		Idle/Throttling support is available
       		Virtual Hard Disk (VHD) support
       		Asynchronous I/O support
       		Asynchronous Clock support
       		FrontPanel API Version 4
       	Host Platform:
       		Compiler: GCC 4.2.1 Compatible Apple LLVM 8.0.0
       		(clang-800.0.42.1)
       		Simulator Compiled as C arch: x64 (Release Build) on Mar
       		 8 2017 at 19:55:19
       		Memory Access: Little Endian
       		Memory Pointer Size: 64 bits
       		Large File (>2GB) support
       		SDL Video support: No Video Support
       		PCRE RegEx support for EXPECT commands
       		OS clock resolution: 1ms
       		Time taken by msleep(1): 1ms
       		OS: Darwin maelona.local 16.4.0 Darwin Kernel Version
       		16.4.0: Thu Dec 22 22:53:21 PST 2016;
       		root:xnu-3789.41.3~3/RELEASE_X86_64 x86_64
        git commit id: b41d10f1

Excerpt from kernel config: 
device          dhu0    at uba? csr 0160440             vector dhurint
dhuxint

Is it a config error?

-- 
  Cory Smelosky
  b4 at gewt.net


More information about the Simh mailing list