[Simh] FPP8A

[Ray Jewhurst]

I know I should have specified and I do apologize.  This aspect of
simulation is quite new to me and I'm both trying to learn how the
simulator works and to a lesser extent the simh and DEC vernacular.  I am
helping out with this project for several reason.  First and foremost, I
want to give back to the team that has given me years of enjoyment trying
out computer systems that until I found out about simh barely knew
existed.  Also, I emulate/simulate for historic preservation.  I believe
that you can appreciate the new even more if you know about the old.
Lastly, I am doing this for educational purposes both learning programming
and learning history.  As funny as may sound with my experience with such
programs I'm probably better versed in the theory behind assembly languages
than I am the higher level ones.  Sorry if this is a bit OT but I just want
to thank you all for allowing me this opportunity.

Thanks
Ray

On Sat, Apr 9, 2016 at 6:53 PM, Rick Murphy <simh at rickmurphy.net> wrote:

> At 03:08 PM 4/9/2016, Ray Jewhurst wrote:
>
> Thanks Bob, this will help me a great deal. A question though, everything
>> I've read has been for the PDP -8/A.  Doesn't simh simulate the E?
>>
>
> The FPP-8A was the Omnibus implementation of the FPP for the PDP-8 series.
> It'd work just fine with an KK8E or a KK8A main CPU card. It was a hex
> height board, so it required an 8/A chassis.
>
> I'm sort of agreeing with Johnny here - you're asking about internals of
> the simulator rather than the registers managed by the actual hardware.
>
> The FPP is a separate CPU with a completely different instruction set that
> happens to be able to be connected to the Omnibus and can be commanded by
> the main PDP-8 CPU, and which can run independently of the main CPU
> executing instructions read out of the same memory as the main CPU. It's a
> 15 bit CPU (pointers are 15 bits wide). The largest accumulator size is 72
> bits (Extended precision mode, 12 bit exponent and 60 bit mantissa).
>
> For the fpp-8a implementation in SIMH, here's the registers you mentioned -
>                                             // Floating point accumulator:
>     { ORDATA (FPACE, fpp_ac.exp, 12) }, // Exponent
>     { ORDATA (FPAC0, fpp_ac.fr[0], 12) },       // First mantissa word
>     { ORDATA (FPAC1, fpp_ac.fr[1], 12) },       // Second mantissa word
>     { ORDATA (FPAC2, fpp_ac.fr[2], 12) },       // etc.
>     { ORDATA (FPAC3, fpp_ac.fr[3], 12) },
>     { ORDATA (FPAC4, fpp_ac.fr[4], 12) },
>     { ORDATA (CMD, fpp_cmd, 12) },              // FPP command register[1]
>     { ORDATA (STA, fpp_sta, 12) },              // Status register
>     { ORDATA (APTA, fpp_apta, 15) },            // Active Parameter Table
> (APT) pointer[2]
>     { GRDATA (APTSVF, fpp_aptsvf, 8, 3, 12) },  // APT field
>     { ORDATA (FPC, fpp_fpc, 15) },              // FPP Program counter
>     { ORDATA (BRA, fpp_bra, 15) },              // Base address
>     { ORDATA (XRA, fpp_xra, 15) },              // Pointer to index
> register zero
>     { ORDATA (OPA, fpp_opa, 15) },              // Operand pointer
>     { ORDATA (SSF, fpp_ssf, 12) },              // Single-step flag
>     { ORDATA (LASTLOCK, fpp_last_lockbit, 12) },// Lockout bit from
> FPCOM[3]
>     { FLDATA (FLAG, fpp_flag, 0) },             // Done flag
>
> [1] The command register sets the initial operating state of the FPP when
> the FPST IOT (FPP Start) is executed.
>
> [2] The APT has the field bits for the base, index, operand, and FPC
> addresses, as well as the low 12 bits of each of those. It also has the
> FAC. Upon startup, the APT tells the FPP CPU where to get going; when it
> halts, the APT is updated.
>
> [3] The "lockout" bit, if set when a PDP-8 FPCOM loads the command
> register, tells the FPP-8A to lock out the PDP-8 CPU if possible. If
> lockout is not enabled, the FPP will interleave access to memory with the
> PDP-8 CPU.
>         -Rick
>
>
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