[Simh] RD53 image size
Bob Supnik
bob at supnik.org
Thu May 7 12:45:33 EDT 2015
With your assumptions. The RD53 has 138672 logical blocks. 138672 * 512
= 71,000,064. This is less than the actual physical capacity because the
controller reserves some amount of space for bad block tables and
replacement blocks. See the attached document, chapter 3, for details.
The same is true of the RD52. It is actually 512 cylinders, not 480, and
the visible capacity is a subset of the physical capacity. There were
two different vendor drives used, one with 8 surfaces, one with 7, and
the capacity is limited to what the 7 surface drive could hold.
/Bob Supnik
On 5/7/2015 12:00 PM, simh-request at trailing-edge.com wrote:
> Message: 1
> Date: Wed, 6 May 2015 22:29:24 -0500
> From: Seth Morabito<lists+simh at loomcom.com>
> To:simh at trailing-edge.com
> Subject: [Simh] RD53 image size
> Message-ID:<20150507032924.GA21046 at loomcom.com>
> Content-Type: text/plain; charset=us-ascii
>
> Hello all,
>
> I'm trying to build an RD53 image that I can transfer to a real RD53
> on an 11/73. I did the same with an RD52 on another system and it
> worked perfectly, but I noticed something odd about the RD53.
>
> The RD52 image size is 30,965,760 bytes. That maps exactly to 480
> cylinders, 7 heads, 18 sectors/cylinder, 512 bytes per sector.
> (480 * 7 * 18 * 512 = 30965760).
>
> The RD53 image that SIMH generates, on the other hand, is 71,000,064
> bytes. This does not match what I would expect. The RD53 is 1024
> cylinders, 8 heads, 17 sectors/cylinder, 512 bytes per sector. That
> should be 71,303,168 bytes, shouldn't it?
>
> Is something wrong with my math, or one of my assumptions?
>
> -Seth
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| DIGITAL EQUIPMENT CORPORATION |
| MAYNARD, MASSACHUSETTS |
| |
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| ENGINEERING SPECIFICATION DATE: 09-JUN-1986 |
| |
| |
|-----------------------------------------------------------------------|
| Title: RQDX3 Engineering Specification |
| |
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| Revisions |
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| Rev | Description | Chg No | Orig | Date | Appd By | Date |
|-----------------------------------------------------------------------|
| A | First Release | | | | | |
| B | Add New Devices | | | | | |
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|-----------------------------------------------------------------------|
| Eng: | Appd: | Size | Code | Number | Rev |
| | |-------|-------|-------------|---------|
| Nick A. Warchol | | K | SP | RQDX3-0-DBF | A |
| | | | | | |
|-----------------------------------------------------------------------|
| This document and the specifications contained herein are |
| confidential and proprietary. They are the property of Digital |
| Equipment Corporation and shall not be reproduced or copied or |
| used in whole or in part as the basis for the manufacture or |
| sale of items without written permission. This is an un- |
| published work protected under the federal copyright laws. |
| COPYRIGHT (C) 1985, DIGITAL EQUIPMENT CORPORATION |
| |
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ENGINEERING SPECIFICATION DIGITAL Page 2
RQDX3 Engineering Specification RQDX3-0-DBF
RQDX3 Engineering Specification
REV. 2.0 09-JUN-1986
Nick A. Warchol
Stephen F. Shirron
C O M P A N Y C O N F I D E N T I A L
Copyright (c) 1985, 1986 by Digital Equipment Corporation
The information in this document is subject to change
without notice and should not be construed as a commitment
by Digital Equipment Corporation. Digital Equipment
Corporation assumes no responsibility for any errors that
may occur in this document.
ENGINEERING SPECIFICATION DIGITAL Page 3
RQDX3 Engineering Specification RQDX3-0-DBF
CONTENTS
1 ABOUT THIS DOCUMENT . . . . . . . . . . . . . . . . 5
2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . 5
3 HARDWARE . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Architecture . . . . . . . . . . . . . . . . . . . 5
3.2 Performance optimizations . . . . . . . . . . . . 6
3.2.1 Elimination of Hard Disk Sector Interleave . . . . 6
3.2.2 Elevator Seek Algorithm . . . . . . . . . . . . . 6
3.2.3 Buffered Seeks . . . . . . . . . . . . . . . . . . 7
3.2.4 Overlapped Seeks . . . . . . . . . . . . . . . . . 7
3.2.5 Physical Sector Skew . . . . . . . . . . . . . . . 7
3.2.6 Error Correction . . . . . . . . . . . . . . . . . 7
3.3 Write Precompensation . . . . . . . . . . . . . . 8
3.4 Devices and Geometries . . . . . . . . . . . . . . 8
3.4.1 Supported Configurations . . . . . . . . . . . . . 8
3.4.2 Formatting . . . . . . . . . . . . . . . . . . . . 8
3.4.3 RD54 . . . . . . . . . . . . . . . . . . . . . . 10
3.4.4 RD53 . . . . . . . . . . . . . . . . . . . . . . 11
3.4.5 RD52 . . . . . . . . . . . . . . . . . . . . . . 12
3.4.6 RD51 . . . . . . . . . . . . . . . . . . . . . . 13
3.4.7 RD31 . . . . . . . . . . . . . . . . . . . . . . 14
3.4.8 RX50 . . . . . . . . . . . . . . . . . . . . . . 15
3.4.9 RX33 . . . . . . . . . . . . . . . . . . . . . . 16
4 FIRMWARE . . . . . . . . . . . . . . . . . . . . . 16
4.1 Disk Geometry . . . . . . . . . . . . . . . . . 16
4.2 Data Structures . . . . . . . . . . . . . . . . 16
4.3 T11 Functional Code . . . . . . . . . . . . . . 18
4.3.1 MSCP Implementation Specifics . . . . . . . . . 19
4.3.1.1 Unit Flags . . . . . . . . . . . . . . . . . . . 20
4.3.1.2 Controller Flags . . . . . . . . . . . . . . . . 21
4.3.1.3 Opcodes . . . . . . . . . . . . . . . . . . . . 22
4.3.1.4 Command Modifiers . . . . . . . . . . . . . . . 23
4.3.1.5 Attention Messages . . . . . . . . . . . . . . . 25
4.3.1.6 Error Log Messages . . . . . . . . . . . . . . . 25
4.3.2 DUP Implementation Specifics . . . . . . . . . . 25
4.3.2.1 Opcodes . . . . . . . . . . . . . . . . . . . . 25
4.3.3 UQSSP Implementation Specifics . . . . . . . . . 26
4.3.3.1 Options . . . . . . . . . . . . . . . . . . . . 26
5 DIAGNOSTICS . . . . . . . . . . . . . . . . . . . 27
5.1 Local Diagnostics . . . . . . . . . . . . . . . 27
5.2 Field Service Invoked Tests . . . . . . . . . . 27
6 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . 28
6.1 Q22 Bus Loading . . . . . . . . . . . . . . . . 28
6.2 Power Requirements . . . . . . . . . . . . . . . 28
7 ENVIRONMENTAL AND RELIABILITY . . . . . . . . . . 28
8 PHYSICAL SPECIFICATIONS . . . . . . . . . . . . . 29
8.1 Module Finger Connections . . . . . . . . . . . 29
8.2 Connector Pinout . . . . . . . . . . . . . . . . 30
8.3 Connector Signal Description . . . . . . . . . . 31
8.4 Jumper Configuration . . . . . . . . . . . . . . 35
ENGINEERING SPECIFICATION DIGITAL Page 4
RQDX3 Engineering Specification RQDX3-0-DBF
APPENDIX A Applicable Documents
ENGINEERING SPECIFICATION DIGITAL Page 5
RQDX3 Engineering Specification RQDX3-0-DBF
1 ABOUT THIS DOCUMENT
The purpose of this document is to describe the
capabilities of the RQDX3 disk controller, specify its
software and hardware interfaces, and give a brief
description of how the controller performs its functions.
It is not intended to be a description of the internals of
the controller; for that detail the reader should refer to
both the RQDX3 Technical Description and the documentation
drawings for the module (M7555).
2 INTRODUCTION
The RQDX3 is a dual height module that interfaces up to
four logical disk units to the Q22 bus. These units can
be RD31, RD51, RD52, RD53, or RD54 hard disk drives, 250
kHz data rate RX50 floppy disk drives, or 500 kHz data
rate RX33 floppy disk drives. The controller also
contains the logic to support a disk system front panel.
The controller supports the MSCP protocol, the DUP
protocol and the U/Q port protocol. Performance is
optimized by the use of block mode DMA transfers on the
Q22 bus, a 1-to-1 sector interleave on the hard disk
drives, and the use of the microprocessor to perform seek
optimizations. The controller supports command retries,
error correction, and controller initiated bad block
replacement on hard disk drives to improve data
reliability.
Cost has been kept low through the use of an available LSI
disk controller, gate array devices for most of the data
path, and a T11 microprocessor.
3 HARDWARE
3.1 Architecture
The heart of the controller architecture is a three-port
8k word RAM buffer that allows predictable access by the
Qbus DMA engine, the T11 microprocessor, and the disk
controller port. This buffer is large enough to hold a
full track of disk data plus microprocessor workspace.
This multiport architecture permits the parallel operation
of host data transfers, disk data transfers, and
microprocessor access to local data structures for maximum
performance.
ENGINEERING SPECIFICATION DIGITAL Page 6
RQDX3 Engineering Specification RQDX3-0-DBF
The majority of the data path functions are contained in
two CMOS gate array devices. These devices contain all
the registers and latches required to implement the three
ported memory system, the registers required by the U/Q
port, support logic for the Qbus DMA machine and the T11
microprocessor, and the digital logic for the disk data
separator.
3.2 Performance optimizations
It is a goal of the architecture to provide the mechanisms
for various optimizations in order to improve overall
system performance. The following optimizations have been
included in the controller design.
3.2.1 Elimination of Hard Disk Sector Interleave -
The current RQDX1 and RQDX2 disk controllers use a 3-to-1
sector interleave of logical disk blocks. This has the
effect of requiring an average of 3.5 revolutions to
transfer a single track. This has been proven to be a
very poor characteristic of those controllers when
attached to MicroVax systems.
The RQDX3 has eliminated this data transfer problem. The
architecture of the controller has been designed to allow
a 1-to-1 sector interleave on the disk surface bringing
the maximum average transfer time for one track to 1.5
revolutions. This was accomplished through the use of a
multiport memory structure that allows simultaneous
operation of disk data transfers and Qbus DMA data
transfers.
It should be noted that disk drives currently operating
with an RQDX1 or RQDX2 controller will NOT be FORMAT
COMPATIBLE with this controller. Before being used with
this controller they MUST BE BACKED UP TO ANOTHER MEDIA,
AND THEN REFORMATTED AND REWRITTEN WITH THIS CONTROLLER.
In order to provide the same maximum storage capacity for
the RD51 drive as is currently available with the RQDX1
and RQDX2 controllers, a 2-to-1 sector interleave will be
used with the RD51 drive.
3.2.2 Elevator Seek Algorithm -
ENGINEERING SPECIFICATION DIGITAL Page 7
RQDX3 Engineering Specification RQDX3-0-DBF
This optimization operates the actuator arm of the disk in
the same manner as an elevator in a building is operated.
When the arm is moving in one direction all transfers that
can be performed while moving in that same direction will
be serviced, and those that would require a change in arm
direction will be postponed. When the actuator arm
reaches a limit, the direction is reversed. This seek
reordering can be overridden on a per-command basis.
3.2.3 Buffered Seeks -
The hard disk interface provides for buffered seek
operations. All the required step pulses for the drive
can be sent to the drive in a short period of time, the
drive will then increase the rate of actuator arm movement
in order to provide a faster average seek rate.
3.2.4 Overlapped Seeks -
When multiple hard disk drives are attached to the
controller, the seek pulses for each drive will be sent
without waiting for a seek complete indication from the
drive. The drives will then be polled for the first seek
completion at which time that data transfer operation
pending for that drive will be performed. This will allow
a percentage of the seek time to be overlapped with data
transfers on another drive.
3.2.5 Physical Sector Skew -
The mapping of logical data blocks to physical disk
sectors will incorporate a skew between surfaces and
cylinders. The amount of skew is specified at format time
to allow the most efficient transfer of contiguous logical
data blocks for the particular drive in use.
3.2.6 Error Correction -
All data will be written with either CRC or ECC appended.
The controller will perform retries to eliminate soft data
errors. If a reasonable number of retries cannot correct
the error then it will be considered a hard data error.
For hard disk drives an attempt will be made to correct
this error using the ECC value calculated when the data
were written. The ECC algorithm is capable of detecting
ENGINEERING SPECIFICATION DIGITAL Page 8
RQDX3 Engineering Specification RQDX3-0-DBF
up to an 11-bit error within a sector. Because of the
possibility of miscorrection with the error correction
polynomial used (x^32 + x^23 + x^21 + x^11 + x^2 + 1) only
single bit correction is performed by the controller.
It should be noted that the error correction code can only
be used for protection of the data fields on hard disk
drives. Sector headers for both hard and floppy disks and
the data fields of the floppy disks are protected with a
CRC code. The polynomial used in the CRC calculation is
x^16 + x^12 + x^5 + 1.
Errors on hard disk drives that indicate that a sector is
defective will cause the sector to be replaced with on of
the available replacement blocks. Future accesses to the
defective sector will automatically be revectored to the
replacement block. The total number of replacement blocks
on a drive is dependent upon the drive capacity and is
specified at format time.
3.3 Write Precompensation
Inner tracks of the disk media surfaces must be written
with write precompensation to overcome the bit shift at
the higher flux densities. The controller will write the
data with the required amount of precompensation depending
upon the current disk track in use.
The use of write precompensation is drive dependent and
listed in section 3.4 for each of the supported drive
types.
3.4 Devices and Geometries
3.4.1 Supported Configurations -
The RQDX3 is capable of supporting 4 logical disk units
with up to 16 surfaces per unit and 2048 tracks per
surface. The module contains enough logic to support a
system front panel for 4 hard disk drives. The front
panel support for each hard disk drive is a Ready light
and switch and a Write Protect light and switch. There is
no front panel support for floppy disk drives.
3.4.2 Formatting -
ENGINEERING SPECIFICATION DIGITAL Page 9
RQDX3 Engineering Specification RQDX3-0-DBF
The RQDX3 will eliminate the problem of controller
microcode ECOs when new hard disk devices must be
supported. At disk format time the host resident
formatter program will pass the drive geometry and
characteristics to the controller. These parameters can
either be obtained from a menu driven selection of
currently available DEC drives, or from answers to
specific questions about the drive. The latter method
will allow new drives to be immediately used or will allow
OEM customers to use the drives of their choice. These
drive parameters will be used to format the disk
surface(s) and then will be written to a reserved sector
on a surface that can be found in a common way across all
drives. The controller will then be able to obtain these
parameters from the drive itself instead of from ROM based
tables.
Formatting is supported for all hard disk drives and for
RX33 media. RX50 media must be preformatted to guarantee
media interchange due to uncontrollable speed variations
within the floppy disk drives.
ENGINEERING SPECIFICATION DIGITAL Page 10
RQDX3 Engineering Specification RQDX3-0-DBF
3.4.3 RD54 -
Maxtor
Sector Interleave 1:1
Bytes/sector: 512
Sectors/LBN: 1
LBNs/track: 17
Tracks/group: 15
Groups/cylinder: 1
Cylinders/unit: 1225
Total LBNs/unit: 312375
RBNs/unit: 609
RCT size(blocks): 7
RCT copies: 8
DBNs/unit: 201
XBNs/unit: 54
User LBNs/unit: 311200
User capacity(bytes): 159,334,400
Step Pulse Width(usec) 11.2
Step Rate(usec) 17.6
Write Precomp none
ENGINEERING SPECIFICATION DIGITAL Page 11
RQDX3 Engineering Specification RQDX3-0-DBF
3.4.4 RD53 -
Micropolis
Sector Interleave 1:1
Bytes/sector: 512
Sectors/LBN: 1
LBNs/track: 17
Tracks/group: 8
Groups/cylinder: 1
Cylinders/unit: 1024
Total LBNs/unit: 139264
RBNs/unit: 280
RCT size(blocks): 5
RCT copies: 8
DBNs/unit: 82
XBNs/unit: 54
User LBNs/unit: 138672
User capacity(bytes): 71,000,064
Step Pulse Width(usec) 11.2
Step Rate(usec) 17.6
Write Precomp none
ENGINEERING SPECIFICATION DIGITAL Page 12
RQDX3 Engineering Specification RQDX3-0-DBF
3.4.5 RD52 -
Quantum Atasi
Sector Interleave 1:1 1:1
Bytes/sector: 512 512
Sectors/LBN: 1 1
LBNs/track: 17 17
Tracks/group: 8 7
Groups/cylinder: 1 1
Cylinders/unit: 512 645
Total LBNs/unit: 69632 76755
RBNs/unit 168 168
RCT size(blocks): 4 4
RCT copies: 8 8
DBNs/unit: 82 65
XBNs/unit: 54 54
User LBNs/unit: 60480 60480
User capacity(bytes): 30,965,760 30,965,760
Step Pulse Width(usec) 11.2 11.2
Step Rate(usec) 17.6 17.6
Write Precomp(nsec) 10 10
Precomp cylinders 256-511 320-644
ENGINEERING SPECIFICATION DIGITAL Page 13
RQDX3 Engineering Specification RQDX3-0-DBF
3.4.6 RD51 -
Seagate
Sector Interleave 2:1
Bytes/sector: 512
Sectors/LBN: 1
LBNs/track: 18
Tracks/group: 1
Groups/cylinder: 4
Cylinders/unit: 306
Total LBNs/unit: 22032
RBNs/unit 144
RCT size(blocks): 36
RCT copies: 4
DBNs/unit: 87
XBNs/unit: 57
User LBNs/unit: 21,600
User capacity(bytes): 11,059,200
Step Pulse Width(usec) 11.2
Step Rate(usec) 17.6
Write Precomp(nsec) 10
Precomp cylinders 110-305
ENGINEERING SPECIFICATION DIGITAL Page 14
RQDX3 Engineering Specification RQDX3-0-DBF
3.4.7 RD31 -
Seagate
Sector Interleave 1:1
Bytes/sector: 512
Sectors/LBN: 1
LBNs/track: 17
Tracks/group: 4
Groups/cylinder: 1
Cylinders/unit: 615
Total LBNs/unit: 41820
RBNs/unit: 100
RCT size(blocks): 3
RCT copies: 8
DBNs/unit: 14
XBNs/unit: 54
User LBNs/unit: 41560
User capacity(bytes): 21,278,720
Step Pulse Width(usec) 11.2
Step Rate(usec) 17.6
Write Precomp none
ENGINEERING SPECIFICATION DIGITAL Page 15
RQDX3 Engineering Specification RQDX3-0-DBF
3.4.8 RX50 -
Sector Interleave 2:1
Bytes/sector: 512
Sectors/LBN: 1
LBNs/track: 10
Tracks/group: 80
Group/cylinder: 1
Cylinders/unit: 1
Total LBNs/unit: 800
RBNs/track: 0 (not supported)
RCT size: 0 (not supported)
RCT copies: 0 (not supported)
DBNs/unit: 0 (not supported)
User LBNs/unit: 800
User capacity(bytes): 409,600
Step Pulse Width(usec) 224
Step Rate(msec) 8
Write Precomp +/- 110 nsec cylinders 0-55
+/- 210 nsec cylinders 56-79
ENGINEERING SPECIFICATION DIGITAL Page 16
RQDX3 Engineering Specification RQDX3-0-DBF
3.4.9 RX33 -
Sector Interleave 1:1
Bytes/sector: 512
Sectors/LBN: 1
LBNs/track: 15
Tracks/group: 2
Group/cylinder: 1
Cylinders/unit: 80
Total LBNs/unit: 2400
RBNs/track: 0 (not supported)
RCT size: 0 (not supported)
RCT copies: 0 (not supported)
DBNs/unit: 0 (not supported)
User LBNs/unit: 2400
User capacity(bytes): 1,228,800
Step Pulse Width(usec) 112
Step Rate(msec) 4
Write Precomp +/- 210 nsec cylinders 0-79
4 FIRMWARE
4.1 Disk Geometry
Hard disk drives may have various numbers of XBNs, DBNs,
LBNs, and RBNs. The number of each may be set during
format time, according to the following constraints. The
RQDX3 firmware requires XBNs to store drive-specific
characteristics and to implement the track-reformatting
required to efficiently handle bad block revectoring; in
each copy, a single sector is used to store the
aforementioned characteristics and an entire track is
required to store the data belonging to a specific track
being reformatted during bad block replacement. For
redundancy three copies of the XBN structure are used.
Diagnostic programs will require access to an area of the
disk reserved for this purpose, in order to perform
diagnostic reads and writes; a certain minimum number of
DBNs are set aside for this purpose. The major portion of
the disk consists of LBNs, which the host uses to store
data and which the controller uses to store the RCT. The
remaining area on the disk is used for RBNs, which are
sectors set aside to replace failing sectors in the LBN
space.
4.2 Data Structures
Before entering a description of the layers of the
firmware, it is important to understand what the firmware
is trying to do and the data structures which allow
communication between these functional blocks.
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RQDX3 Engineering Specification RQDX3-0-DBF
The function of the RQDX3 firmware is to control the Q-bus
DMA engine and the SMC9224 disk controller chip on behalf
of a host. The firmware obtains command packets from the
host, checks their validity, directs the hardware to
perform the required tasks, and finally informs the host
of the success or failure of these tasks via response
packets. The firmware also operates the front panel
(i.e., the human interface). To perform these tasks and
several others, the firmware uses blocks of RAM to hold
host commands and associated responses, to maintain disk
drive status and controller status, to communicate with
the other two subsystems, and to perform internal
bookkeeping between competing requests and external
events. The RQDX3 firmware uses the following data
structures:
o Command and Response Ring Description Blocks
These are small blocks of RAM which contain pointers
into the host command and response rings, the size of
these rings, and which packet within the ring is
currently active.
o Command and Response Packets
These are fixed length blocks of RAM containing a host
command or response. Packet offsets are in the form
P.offset for MACRO code and P_offset for C code. Thus
the unit number in the packet may be referenced as
P.UNIT (or P_UNIT).
o Sector Buffers
These are large, fixed length blocks of RAM used as
intermediate buffers for data being read from or
written to disk by the SMC9224. During a read, the
sector buffer is filled by the Q-bus DMA engine and
later emptied by the SMC9224 chip; during a write, the
sector buffer is filled by the SMC9224 chip and is
later emptied by the Q-bus DMA engine.
o Controller and Unit Control Blocks
These are fixed length blocks of RAM containing the
current status of the controller and of each of the
attached disk drives. These contain all information
needed to perform any given task. Some of this
information may be read by the host (with appropriate
commands) and some may be written. For example, the
drive geometry information is returned in the GET UNIT
STATUS command, while controller flags may be both
read and written with the SET CONTROLLER
CHARACTERISTICS command.
ENGINEERING SPECIFICATION DIGITAL Page 18
RQDX3 Engineering Specification RQDX3-0-DBF
o Queues
These are structures which link together other related
control structures. For example, the Q-bus DMA engine
and the SMC9224 disk controller chip both maintain
queues of work to do, and as required extract the
highest priority tasks from their respective queues
and start them going. Two distinct types of queues
are used in the RQDX3 firmware. When order within a
queue is either unimportant (e.g., a queue of empty
packets) or is priority ordered (e.g., a queue of
transfers to perform), a singly linked list is used
(only a "listhead" is needed). When a queue must be
handled in FIFO order (e.g., a queue of sequential
MSCP packets), an additional piece of information is
required (the "listtail") for efficiency.
4.3 T11 Functional Code
The T11 firmware can be broken down into major functional
sections:
o Operating System Code
The operating system code serves as the outermost
control structure and handles dispatching to the other
functional sections.
o UQSSP Code
The UQSSP code handles communication between the host
and the T11 via the IP and SA registers, and also
manages the reception of command packets from the host
and transmission of response packets to the host.
o MSCP Code
The MSCP code performs all associated handling of MSCP
command and response packets, including verification
of fields and initiation of data transfers. It also
generates log packets for serious errors.
o DUP Code
The DUP code performs all associated handling of DUP
command and response packets. It manages the running
of diagnostic programs (either local or loadable).
o Low-Level Disk I/O Code
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RQDX3 Engineering Specification RQDX3-0-DBF
The low-level disk I/O code is responsible for
communicating with both the Q-bus DMA engine and the
SMC9224 chip, initiating transfers to disk and to
memory. It handles error detection and recovery.
The RQDX3 firmware consists of a set of cooperating
routines ("jobs") which each perform dedicated functions.
Each job has its own stack and thus its own context. Any
operations which could possibly run in parallel have been
separated, and are controlled by separate jobs. Jobs
block and unblock one another as they hand tasks back and
forth; unblocking can also be done by interrupt service
routines.
The MAIN job creates the other jobs and handles various
timer functions. It is the lowest priority job and will
only run when all other jobs are blocked.
The POLL job polls the host communications area in
response to an IP read, gathers any available commands,
and dispatches to either MSCP or DUP, which in turn
dispatch on the given opcode to individual routines (e.g.,
READ, WRITE, or SEND DATA). These latter routines either
complete the requested operation immediately or else
insert the request onto the right queue and unblock some
other job.
The SCAN job periodically wakes up and checks front panel
status for each of the units; this catches floppy disk
door transitions (open/close, close/open) and
online/offline transitions.
Each unit (i.e., disk drive) has a WORK job which scans
for either additional transfers to perform or additional
packets to decode. These jobs are responsible for
selecting the optimal transfer to perform based on the
elevator seek algorithm; if more than one unit has an
available transfer, then seeks are started in parallel on
each of the units.
4.3.1 MSCP Implementation Specifics -
The RQDX3 supports all of MSCP, with the following major
additions and omissions: controller-initiated bad block
replacement is implemented; caching, shadowing, multi-host
support, data encryption, and the REPLACE and ACCESS
NON-VOLATILE MEMORY commands are not implemented.
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4.3.1.1 Unit Flags -
The following unit flags are supported by the RQDX3:
o Compare Reads
If this flag is set by the host, all READ commands are
followed by compare operations (see the command
modifier "Compare").
o Compare Writes
If this flag is set by the host, all WRITE commands
are followed by compare operations (see the command
modifier "Compare").
o Controller-Initiated Bad Block Replacement
This flag being set by the controller signals the host
that it will never have to perform bad block
replacement on behalf of the controller.
o Removable Media
This flag is set by the controller for floppy disks
and is cleared for hard disks.
o Write Protect (hard)
This flag is set by the controller when it detects
that the unit is hardware write-protected.
o Write Protect (soft)
This flag is set by the host to disable write
operations to the unit.
o 576-Byte Sectors
This flag is cleared by the controller since it does
not support 576-byte sectors.
The following unit flags are not supported by the RQDX3:
o Inactive Shadow Set
This flag is ignored by the controller since it does
not support shadowing.
o Suppress Caching, Write-Back/Write-Through
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RQDX3 Engineering Specification RQDX3-0-DBF
These flags are ignored by the controller since it
does not support caching.
4.3.1.2 Controller Flags -
The following controller flags are supported by the RQDX3:
o Enable Attention Messages
This flag is set by the host if it wants the
controller to send any and all attention messages.
Attention messages are generated by asynchronous
events.
o Enable This Host's Error Log Messages
This flag is set by the host if it wants the
controller to send any and all error log messages.
Error log messages are generated by synchronous
events.
o Controller-Initiated Bad Block Replacement
This flag being set by the controller signals the host
that it will never have to perform bad block
replacement on behalf of the controller.
o Shadowing
This flag is cleared by the controller since it does
not support shadowing.
o 576-Byte Sectors
This flag is cleared by the controller since it does
not support 576-byte sectors.
o Multi-Host Support
This flag is cleared by the controller since it does
not support multiple hosts.
o Caching
This flag is cleared by the controller since it does
not support caching.
The following controller flags are not supported by the
RQDX3:
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o Enable Miscellaneous Error Log Messages
This flag is ignored by the controller since it never
generates miscellaneous error log messages.
o Enable Other Host's Error Log Messages
This flag is ignored by the controller since it does
not support multiple hosts.
4.3.1.3 Opcodes -
The following opcodes are supported by the RQDX3:
o SET CONTROLLER CHARACTERISTICS
o ABORT
o AVAILABLE
o ONLINE
o GET COMMAND STATUS
o GET UNIT STATUS
o SET UNIT CHARACTERISTICS
o READ
o WRITE
o COMPARE
o ACCESS
o ERASE
The following opcodes are supported by the RQDX3 but are
no-ops:
o COMPARE CONTROLLER DATA
o DETERMINE ACCESS PATHS
o FLUSH
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RQDX3 Engineering Specification RQDX3-0-DBF
The following opcodes are not supported by the RQDX3:
o ACCESS NON-VOLATILE MEMORY
o REPLACE
4.3.1.4 Command Modifiers -
All transfer commands (READ, WRITE, COMPARE, ACCESS, and
ERASE) support the following command modifiers:
o Compare
This modifier requests that a compare operation be
performed after the initial operation is complete.
This is accomplished by (re)obtaining the data from
the host buffer, (re)obtaining the data from the disk,
and comparing the two. Any pair of bytes which fails
to match causes the command to terminate with an
error.
o Express Request
This modifier requests that the controller ignore its
usual optimization procedures and complete the command
as quickly as possible. This is accomplished by
inserting this request at the head of the transfer
queue, ignoring the elevator seek algorithm.
o Force Error
This modifier requests that the controller mark the
blocks to be written as questionable. This is
accomplished by performing the write operation with
the "write deleted data mark" modifier set; when the
blocks are subsequently read back, this information is
recovered and returned to the host.
o Suppress Error Correction
This modifier requests that the controller not try to
correct any block which is read with an ECC error.
This is accomplished by omitting the error correction
step in the low-level disk read/write routine.
o Suppress Error Recovery
This modifier requests that the controller not try to
recover any block which has an initial error. This is
accomplished by setting the number of allowable
retries in the low-level disk read/write routine to
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RQDX3 Engineering Specification RQDX3-0-DBF
zero, and also by implicitly setting the "Suppress
Error Correction" modifier bit (since correction is
one method of recovery).
The GET UNIT STATUS command supports the following command
modifier:
o Next Unit
This modifier requests that the controller return
status about the next known unit with unit number
greater than or equal to the given unit number. This
is used by host drivers to determine which unit
numbers are known to a given controller.
The SET UNIT CHARACTERISTICS command supports the
following command modifiers:
o Enable Set Write Protect
This modifier requests that the host be allowed to
manipulate the software write protect status of the
unit.
o Shadow Unit Specified
This modifier is not allowed, since shadowing is not
supported. If it is set, an error is returned.
The ONLINE command supports the following command
modifiers:
o Ignore Media Format Error
This modifier requests that the unit be brought online
even if the controller detects some unrecoverable
error (e.g., corrupted RCT) which would normally cause
the unit to remain offline.
o Enable Set Write Protect
Same as under SET UNIT CHARACTERISTICS.
o Shadow Unit Specified
Same as under SET UNIT CHARACTERISTICS.
If a command modifier has not been mentioned here, it is
not supported (i.e., it is ignored).
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4.3.1.5 Attention Messages -
Only the AVAILABLE attention message is ever generated;
this happens when a unit which is Unit-Online
spontaneously transitions to Unit-Available (e.g., after a
bad block replacement attempt fails due to a corrupted
volume, or when the unit is disabled by opening the floppy
disk door or depressing the offline button on the front
panel). The other defined attention messages, ACCESS
PATHS and DUPLICATE UNIT NUMBER, are never generated.
4.3.1.6 Error Log Messages -
The HOST MEMORY ACCESS ERROR, DISK TRANSFER ERROR, and BAD
BLOCK REPLACEMENT ATTEMPT error log messages are all
supported and occasionally generated. The CONTROLLER
error log message is never generated because there are no
known failure modes which are not catastrophic. The SDI
ERROR error log message is never generated since the
controller does not support SDI-type drives.
4.3.2 DUP Implementation Specifics -
The RQDX3 supports all of DUP, with the following major
additions and omissions: running both local and supplied
programs is implemented; concurrent operation with MSCP is
not implemented.
4.3.2.1 Opcodes -
The following opcodes are supported by the RQDX3:
o ABORT PROGRAM
o GET DUP STATUS
o EXECUTE LOCAL PROGRAM
o EXECUTE SUPPLIED PROGRAM
o SEND DATA
o RECEIVE DATA
The status returned by GET DUP STATUS indicates that the
DUP server must run standalone (i.e., it crashes the MSCP
server), that there is a local load media (ROM), and that
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RQDX3 Engineering Specification RQDX3-0-DBF
supplied programs are allowed also. The only local
programs are DIRECTORY and FORMAT; when DIRECTORY is run,
it returns this information.
4.3.3 UQSSP Implementation Specifics -
The RQDX3 supports all of UQSSP, with the following major
additions and omissions: mapped transfers are
implemented; transfers to odd addresses and maintenance
read/write are not implemented.
4.3.3.1 Options -
The following options are communicated to the host during
port initialization:
o Mapped Transfers
The RQDX3 can run on hosts which do not have their own
scatter/gather map.
o Adapter Purges
The RQDX3 can run on hosts which require explicit
adapter purges to flush the cache within the adapter
itself.
o Host-Settable Interrupt Vector
The RQDX3 has a soft interrupt vector, which the host
can set to any value.
o 22-Bit Q-Bus Space
The RQDX3 hardware supports the full 22-bit Q-bus
address space.
o Enhanced Diagnostics
The RQDX3 supports the enhanced diagnostics required
(purge/poll tests, SA register wrap around).
o No Odd Addresses
The RQDX3 hardware cannot transfer to an odd buffer
address.
o No Maintenance Read/Write
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RQDX3 Engineering Specification RQDX3-0-DBF
The RQDX3 does not implement the optional maintenance
read/write commands.
5 DIAGNOSTICS
5.1 Local Diagnostics
Diagnostic tests will be run at power up to give
confidence in module operation. These tests will be
non-destructive to either host memory or user data stored
on the disk surfaces.
The powerup tests will include the following:
o ROM checksum test
o Limited internal register and data path test (non
destructive).
o RAM test in single port mode.
There are also Port Initialization tests that are run when
the host attempts to bring the controller online. These
tests are:
o Qbus DMA test
o Further internal register tests including the disk
controller chip.
o Multiport operation of the memory subsystem.
Successful self diagnostics are indicated with a single
LED on the module. This LED will be on after a Qbus power
up sequence or a Qbus initialization and will be turned
off after the successful completion of the self tests.
5.2 Field Service Invoked Tests
By supporting the Diagnostic and Utility Protocol (DUP) it
will be possible to further test and diagnose the module.
By using the host loadable program feature of DUP it is
possible to load more extensive test programs into the
controller for execution.
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RQDX3 Engineering Specification RQDX3-0-DBF
6 ELECTRICAL SPECIFICATIONS
6.1 Q22 Bus Loading
o 1.9 AC bus loads
o 0.5 DC bus load
6.2 Power Requirements
o 2.48 Amps typical at +5.0 VDC +/- 5%
o 2.90 Amps maximum at +5.0 VDC +/- 5%
o 0.06 Amps typical at +12 VDC +/- 5%
o 0.1 Amps maximum at +12 VDC +/- 5%
7 ENVIRONMENTAL AND RELIABILITY
This module adheres to DEC Standard 102 as a device
capable of operating in a class C environment, although
the actual environment is usually limited by the
mechanical disk drives that this controller interfaces
with.
o Temperature
. Operating +5 to +60 degrees C
. Storage -40 to +66 degrees C
o Humidity
. Operating 10 to 95% non-condensing
. Storage 10 to 95% non-condensing
o Altitude
. Operating 8,000 ft (2.4 Km)
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RQDX3 Engineering Specification RQDX3-0-DBF
Note: De-rate the maximum operating temperature
by 1.8 degrees C for each 1000 meters of altitude
unless constant cooling is provided as air density
changes with altitude.
. Storage 30,000 ft (9.1 Km)
o Airflow, operating
Adequate airflow must be provided to limit the inlet
to outlet temperature rise across the module so the
outlet temperature never exceeds 70 degrees
Centigrade. The typical power dissipation of the
module is such that with a 60 degree C inlet
temperature, this can be achieved with a 4 cubic feet
per minute airflow. No area of the board may be
subjected to a local ambient temperature above 70
degrees C under any environmental conditions.
o MTBF
. Class A - 66,000 hours
. Class B - 29,000 hours
. Class C - 18,000 hours
o Soft Error Rate
. Hard Disk Drives - 1 error in 10^10 bits read
. Floppy Disk Drives - 1 error in 10^8 bits read
Note that "bits read" includes all headers and
checksums read during the seek and data transfer
operation.
8 PHYSICAL SPECIFICATIONS
8.1 Module Finger Connections
Note: Names in the parenthesis are bus signals not used.
AA1 (BIRQ5 L) AA2 +5V
AB1 (BIRQ6 L) AB2 (-12V)
AC1 BDAL16 L AC2 GND
AD1 BDAL17 L AD2 +12
AE1 (SSPARE1 or +5B) AE2 BDOUT L
AF1 (SSPARE2) AF2 BRPLY L
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RQDX3 Engineering Specification RQDX3-0-DBF
AH1 (SSPARE3) AH2 BDIN L
AJ1 GND AJ2 BSYNC L
AK1 (MSPAREA) AK2 BWTBT L
AL1 (MSPAREB) AL2 BIRQ4 L
AM1 GND AM2 BIAKI L
AN1 BDMR L AN2 BIAKO L
AP1 (BHALT L) AP2 BBS7 L
AR1 BREF L AR2 BDMGI L
AS1 (+12B or +5B) AS2 BDMGO L
AT1 GND AT2 BINIT L
AU1 (PSPARE1) AU2 BDAL0 L
AV1 (+5B) AV2 BDAL1 L
BA1 (BDCOK H) BA2 +5V
BB1 BPOK H BB2 (-12V)
BC1 BDAL18 L BC2 GND
BD1 BDAL19 L BD2 +12V
BE1 BDAL20 L BE2 BDAL2 L
BF1 BDAL21 L BF2 BDAL3 L
BH1 (SSPARE8) BH2 BDAL4 L
BJ1 GND BJ2 BDAL5 L
BK1 (MSPAREB) BK2 BDAL6 L
BL1 (MSPAREB) BL2 BDAL7 L
BM1 GND BM2 BDAL8 L
BN1 BSACK L BN2 BDAL9 L
BP1 (BIRQ7 L) BP2 BDAL10 L
BR1 (BEVNT L) BR2 BDAL11 L
BS1 (+12B) BS2 BDAL12 L
BT1 GND BT2 BDAL13 L
BU1 (PSPARE2) BU2 BDAL14 L
BV1 +5V BV2 BDAL15 L
8.2 Connector Pinout
Connector J1: 12-13506-13
PIN # SIGNAL NAME PIN # SIGNAL NAME
J1-1--------MFMWRTDT1 (H) J1-2--------MFMWRTDT1 (L)
J1-3--------GROUND J1-4--------HEADSEL2 (L)
J1-5--------GROUND J1-6--------SEEKCPLT (L)
J1-7--------DRV4RDY (H) J1-8--------WRTFAULT (L)
J1-9--------HEADSEL3 (L)* J1-10-------HEADSEL1 (L)
J1-11-------DRV1RDY (H) J1-12-------DRV3RDY (H)
J1-13-------DRV1WPT (L) J1-14-------DRVSL0ACK (L)
J1-15-------MFMRDDAT0 (H) J1-16-------MFMRDDAT0 (L)
J1-17-------MFMWRTDT0 (H) J1-18-------MFMWRTDT0 (L)
J1-19-------MFMRDDAT1 (H) J1-20-------MFMRDDAT1 (L)
J1-21-------GROUND J1-22-------REDUCWRTI (L)**
J1-23-------DRV3WPT (L) J1-24-------DRVSEL4 (L)
J1-25-------GROUND J1-26-------INDEX (L)
J1-27-------DRV4WPT (L) J1-28-------DRVSEL1 (L)
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RQDX3 Engineering Specification RQDX3-0-DBF
J1-29-------DRVSEL2 (L) J1-30-------DRVSEL3 (L)
J1-31-------DRV2RDY (H) J1-32-------RXMOTORON (L)
J1-33-------GROUND J1-34-------DIRECTION (L)
J1-35-------GROUND J1-36-------STEP (L)
J1-37-------GROUND J1-38-------RXWRTDATA (L)
J1-39-------GROUND J1-40-------WRTGATE (L)
J1-41-------GROUND J1-42-------TRACK0 (L)
J1-43-------DRV2WPT (L) J1-44-------DRVSL1ACK (L)
J1-45-------GROUND J1-46-------RXRDATA (L)
J1-47-------GROUND J1-48-------HEADSEL0 (L)
J1-49-------GROUND J1-50-------READY (L)
* Connected to the HEADSEL3 signal, left open, or grounded via
a jumper on the module.
** The HEADSEL3 signal may be ORed with the REDUCWRTI signal
via a jumper on the module.
8.3 Connector Signal Description
It is recommended that the output signals from this module
be terminated at the far end of a 130 ohm impedance cable
with a single 220/330 resistor divider network. The
maximum allowable cable length when proper termination is
used is 8 ft. It is the responsibility of the system
design engineer to insure the integrity of these output
signals through proper cabling techniques. With the
variable lengths of cables used in different systems and
the various methods of signal distribution some engineers
may choose to violate this specification. It will not be
possible the guarantee the specified soft error rates in
these situations.
The following is a description of the signals available on
the drive interface connector J1. The timing and
electrical characteristics of these signals are compatible
with the signals as specified in the RD31, RD51, RD52,
RD53, RD54, RX33 and RX50 purchase specifications.
o DIRECTION(L) Output
This signal controls the direction of head movement.
When asserted the direction of movement is towards the
spindle (in).
o DRV<4:1>RDY(H) Input/Output
When one or more of these signals is asserted by the
front panel (READY switch open) the controller will
assume that the hard disk drive on the corresponding
DRV<4:1>SEL line is ready for data transfers. When
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RQDX3 Engineering Specification RQDX3-0-DBF
the controller performs a seek function on a hard disk
drive it will force this signal to an unasserted
condition to turn off the READY light on the front
panel for the corresponding drive.
The controller will ignore the state of the
appropriate DRV<4:1>RDY signal when there is a floppy
disk drive attached to a DRV<4:1>SEL line.
o DRV<4:1>WPT(L) Input/Output
These signals, when asserted from the front panel
(Write Protect switch closed), are used to indicate to
the controller that hard disk drive connected to the
corresponding DRV<4:1>SEL line is to be protect
against write operations.
The controller will assert a DRV<4:1>WPT signal to
indicate that the system software has write protected
the hard disk on the corresponding DRV<4:1>SEL line.
The controller will ignore the state of the
appropriate DRV<4:1>WPT signal when there is a floppy
disk drive attached to a DRV<4:1>SEL line.
o DRV<4:1>SEL(L) Output
The controller will assert one of these signals to
select one of four drives for operation.
o DRVSL<1:0>ACK(L) Input
These input signals are asserted by a hard disk drive
to indicate that it has been selected. When either or
both of these signals are asserted the controller will
assume that there is a hard disk drive connected to
the currently active DRV<4:1>SEL line.
o GROUND
The signal return path.
o HEADSEL<3:0>(L) Output
These signals are used to select one of up to sixteen
surfaces on the currently selected drive.
o INDEX(L) Input
This input signal informs the controller that the
currently selected drive is at the beginning of a
track.
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RQDX3 Engineering Specification RQDX3-0-DBF
o MFMRDDAT<1:0>(H) Input
MFMRDDAT<1:0>(L) Input
Data from the hard disk drive surface will be
transmitted to the controller on these differential
signal pairs. The controller will assume that hard
disk drives on DRV1SEL and DRV3SEL will transmit their
data on the MFMRDDAT0 differential pair and that hard
disk drives on DRV2SEL and DRV4SEL will transmit their
data on the MFMRDDAT1 pair.
o MFMWRTDT<1:0>(H) Output
MFMWRTDT<1:0>(L) Output
These differential signal pairs will define the data
to be written to the disk surface when the Write Gate
signal is asserted. There are two sets of these
differential pairs to allow two hard disk drives to be
connected without external logic. Both pairs of
signals will be active at the same time.
o READY/DISK CHANGE(L) Input
This input signal from the drive will indicate the
following:
For hard disk drives it will indicate that when
SEEKCPLT is also asserted the drive is ready to read,
write, or seek.
For RX33 floppy disk drives it will indicate that the
drive has powered up or that media has been removed;
the signal is cleared when the drive is selected,
media is installed, and a STEP pulse is issued to the
drive.
For RX50 floppy disk drives it will indicate that the
front door is closed, and media is present.
o REDUCWRTI/MOTOR SPEED(L) Output
This controller output can be asserted to force a disk
drive to use a low value of write current if
appropriate.
The RX33 floppy disk drive uses this signal to control
the motor speed: if asserted, low speed is selected;
if unasserted, high speed is selected.
o RXMOTORON(L) Output
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RQDX3 Engineering Specification RQDX3-0-DBF
This signal is asserted by the controller to turn on
the floppy disk drive motors.
o RXRDATA(L) Input
This input is the read data channel from the floppy
disk drives.
o RXWRTDATA(L) Output
This output is the write data channel to the floppy
disk drives.
o SEEKCPLT(L) Input
This input signal should be asserted when the
currently selected hard disk drive has completed a
seek function.
o STEP(L) Output
This output signal is used to step the head(s) of the
currently selected floppy disk drive or hard disk
drive.
o TRACK0(L) Input
This input signal from the currently selected hard
disk drive or floppy disk drive will indicate that the
drives head(s) are positioned at track zero.
o WRTFAULT(L) Input
This signal will be asserted from the currently
selected drive for the following reasons:
For hard disk drives this input should be asserted
when a condition exists in a selected drive that
should cause writing to be inhibited. The signal
should remain asserted until the error condition is
corrected and the drive is deselected. Some of these
error conditions include:
. Write current and no write gate, or drive select
and write gate with no write current.
. Multiple heads, no head, or improperly selected
head.
. DC voltages out of tolerance.
. Write gate and Seek Complete deasserted.
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RQDX3 Engineering Specification RQDX3-0-DBF
For floppy disk drives this signal is asserted when a
write protected diskette is present.
o WRTGATE(L) Output
When asserted this controller output signal will turn
on the write drivers of the currently selected drive.
8.4 Jumper Configuration
The installation process for the RQDX3 module is
relatively simple since the standard configuration should
be suitable for most applications. The standard
configuration is as follows:
o Base Address 172150
o Logical Unit Numbers (of drives) = 0 to 3
o Drive cable configured for RQDX1/2 compatibility.
The following rules should be followed to change one or
more of the above characteristics.
o Base Address -- The module base address can be
configured with jumpers W1 (address bit 2) through W11
(address bit 12). A jumper is installed for a match
to a 1 in the corresponding address bit and removed
for a match to a 0. Address bits 13 through 15 will
always be matched to a one (Qbus I/O page). The
standard base address is selected by installing
jumpers W2, W4, W5, W9, and W11.
o Logical Unit Number -- There are six logical unit
number jumpers on the module labeled W12 (LSB) through
W17 (MSB). These jumpers allow the drives to be
configured on a logical unit number boundary of 4.
(ie. A jumper setting of the binary number 3, jumpers
W12 and W13 installed, would configure the drives on
this module to respond to logical unit numbers 12
through 15).
o Cable compatibility -- This jumper should have little
affect until hard disk drives with more that 8
surfaces are used. This jumper allows the fourth head
select signal to be OR tied with the Reduced Write
Current cable signal as required by current system
boxes (jumper across pins 1 and 2 of W23) or put onto
a separate cable signal (jumper across pins 2 and 3 of
W23) for a less restrictive mix of drive types.
APPENDIX A
Applicable Documents
o RQDX3 Technical Description
o RQDX3 User's Guide
o DEC Std 30 (Module Manufacturing Standard)
o DEC Std 102 (Environmental Standard)
o DEC Std 103 (RFI Standard)
o DEC Std 139 (Reliability Standard)
o DEC Std 160 (LSI-11 Bus Specification)
o DEC Std 166 (Disk Format Standard)
o UQSSP (Unibus/Qbus Storage Systems Port Specification)
o MSCP (Mass Storage Control Protocol Specification)
o DUP (Diagnostic and Utility Protocol Specification)
o RX33 Purchase Specification
o RX50 Purchase Specification
o RD51 Purchase Specification
o RD52 Purchase Specification
o RD53 Purchase Specification
o RD54 Purchase Specification
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