[Simh] Non-numeric character in IBM 1620 P & Q addresses

[Bob Supnik]

It's worse than that. The detailed logic is shown on 227-5631-0 pp 
188ff. The decode chart for each decode switch (DSW) is:

DSW 0        0000
DSW 1        0001
DSW 2        0010
DSW 3        X011
DSW 4        X100
DSW 5        X101
DSW 6        X110
DSW 7        X111
DSW 8        1XX0
DSW 9        1XX1

It's quite bizarre, actually. The decode switches are 4-input AND gates 
(sort of), so every decode could have been complete. Instead, the X 
inputs are not wired to anything.

The result is that for invalid digits:

1010        nothing active, because DSW2 decode is complete
1011        DSW 3 and DSW 9 active
1100        DSW 4 and DSW 8 active
1101        DSW 5 and DSW 9 active
1110        DSW 6 and DSW 8 active
1111        DSW 7 and DSW 9 active

So either no core is selected or multiple cores are selected. Now what 
happens? I suspect it's something bad.

/Bob

On 12/24/2015 5:20 PM, Paul Koning wrote:
>> On Dec 23, 2015, at 4:30 PM, Bob Supnik <bob at supnik.org> wrote:
>>
>> There's nothing conditional about the user documentation. The 1965 reference manual says, "MARS (Memory Address Register Storage) Check Light. This light is turned on when a digit in MARS has a parity error or an invalid address. These errors halt the machine immediately."
>>
>> Now the key question is, what's an invalid address? Earlier, the user documentation talks about detecting an address that's too large (high order digit). But an invalid bit combination? Here's what the Customer Engineering Manual has to say: "Near the end of each memory cycle, MAR is checked for invalid digits in the ten-thousands position and for odd parity in each of the five positions." Nothing about checking for invalid bit combinations.
>>
>> So it appears to me that the simulator's definition of "valid" (or invalid) addresses is too strict. Invalid bit combinations are not checked explicitly.
>>
>> Then the question becomes, what does the 1620 actually do with an invalid bit combination (with valid parity) in MAR? I can't understand the core memory matrix selection logic in the CE Manual well enough to figure that out. The decode process is supposed to yield exactly one of 10 select wires for each digit position. For invalid bits, does it still yield just one? More than one? None?
> I would have guessed that a 4 to 10 BCD decoder would not bother with the 8 bit when decoding for lines 2-7, i.e., you'd get the n = 2..7 line if the input is n mod 8.  Judging by the CE Manual on bitsavers (227-5500-2), page 20, that's almost true.  It shows that the decoders for 3 through 7 are 3 input decoders, they don't use the 8 bit.  The decoder for 2 does use the 8 bit, interestingly enough.
>
> So the answer would be: memory address digit pattern 1010 doesn't decode anything but patterns 1011 through 1111 decode as if they were 0011 through 0111.
>
> 	paul
>
>
>