[Simh] Recent bug fixes

[Johnny Billquist]

On 2013-09-17 03:59, Bob Supnik wrote:
> Message: 5
> Date: Fri, 06 Sep 2013 17:40:19 +0200
> From: Johnny Billquist<bqt at softjar.se>
> To:simh at trailing-edge.com
> Subject: Re: [Simh] Various PDP11 fixes and enhancements
> Message-ID:<5229F763.8090807 at softjar.se>
> Content-Type: text/plain; charset=ISO-8859-1; format=flowed
>
> On 2013-09-06 17:13, Bob Supnik wrote:
>
>> 2. RS03/RS04 - third Massbus adapter with RS03/RS04 fixed head disk.
>> Only tested with RT11, as M+ and RSTS/E support requires a unique
>> SYSGENs. Feel free to hack on it.
>
> Is this something specific to a third massbus, or just a case of the
> RS03/RS04 devices as such? I mean, on M+ you can have all type of
> devices on the same massbus.
>
>>>> The Massbus implementation links an RH to a single device type.
>>>> This is an artifact of the simulator, not of real life.
>>>> Three RH adapters allows for 8 RP/RM units, 8 TU units, and 8 RS units.

I see. So simh don't make any distinction between the RM and RP? The 
registers have a couple of differences between these as well, but if I 
remember right, they are only for error recovery, so they won't affect 
normal operation.
But on an 11M system, I'm not sure you can even mix RM and RP on the 
same massbus. (I might be wrong on that one, though. I need to check.)

>> 3. PDP11 CPU - MMR1 no longer tracks changes to the PC. The issue that
>> it should not track changes in floating point instructions is still open.
>
> I wasn't aware of any discussions. Could you, or someone sum it up? Is
> it a question of whether MMR1 should reflect changes to the general
> registers if a FP instruction is aborted? If so, I'm pretty sure they
> should be. I think I have read it somewhere in some documentation, and
> could try and locate it, if that really is the question.
>
> Also, MMR1 might reflect changes to the PC as well, as far as I can read
> documentation... But it's "complicated".
>
>      Johnny
>
>>>> Looking at the J-11 microcode:
>>>> MMR1 does not track FP changes. This is because in early systems, like
>>>> the 11/45, it didn't have enough bits to record an 8 byte register
>>>> change.
>>>> The J-11 goes through great pains to undo register changes before it
>>>> springs a trap or memory management abort.
>>>> Likewise, the J-11 never tracks PC changes in MMR1. The instruction
>>>> stream is read through a special microinstruction, because the hardware
>>>> always prefetches the next instruction word. Even modes 47 and 57,
>>>> which
>>>> make no sense, don't update MMR1.

Aha. So I was looking at the 11/70 processor handbook, which says that 
MMR1 would track changes to the PC on at least that CPU. But since 
change to the PC is not really important anyway I can see that either 
way would work just as fine.

But I don't see the problem with an 8 byte change. MMR1 have 5 bits for 
telling the changed value. This is a signed value, so it should range 
from +15 to -16.
What am I missing???

	Johnny

>
> /Bob Supnik
>
> _______________________________________________
> Simh mailing list
> Simh at trailing-edge.com
> http://mailman.trailing-edge.com/mailman/listinfo/simh