[Simh] [simh] testing simulated CPUs

[Bob Supnik]

This sounds like AXE, the VAX architectural exerciser. AXE had a wide 
variety of tests - 5M or more in each major instruction group - and 
logic for positioning operands and setting up memory management to 
stress paging boundary conditions, unaligned operands, tracing, and 
other special conditions. AXE's limitations were that it couldn't test 
for pipeline-related problems (addressed in later verifiers such as MAX, 
which did multiple instruction sequences), for real-time conditions like 
interrupts or I/O, or for console HALT.

AXE was intended to be run without a reference host. The test cases were 
first run on the reference, and the results added to the test cases as 
the correct answers. AXE could then be run either as a test harness to 
drive a simulator or on new hardware (or simulated hardware). When AXE 
was finally run against SimH VAX, it turned up a couple of corner case 
bugs in the deprecated floating point instructions (POLY, EMOD, ACB).

 From an analysis I did after NVAX, here are all the VLSI VAX microcode 
bugs that made it past tape-out of the first pass chip:

                       uVAX    CVAX    Rigel    NVAX comment
                       ----    ----    -----    ---- -------
Indexed immediate      1 ECO'd out of SRM
Interrupt passive rel  1       1
Interrupt to string            1
LDPCTX                 1 ECO'd out of SRM
POLYG restart          1 ECO'd out of SRM
CALLx cross page               1                       Improved in AXE V15
POPR to SP                     1 Added to AXE V14
MFPR external to memory        2 Added to HCORE
MTPR ASTLVL            1       1 Added to AXE V15
Vectors                                 2 Added to AXE V15
IB prefetch error                       2
IB TB miss error                        1
Halt PC when FPD set                    1       1
Restriction violation                   2
INSV reserved operand                   1
INSV specifier combination                      1 Found by MAX after 
tape-out
MULL2 PSL<v> result                             1
VIC flushing on HALT                            1
Powerup initialization                          1

As can be seen, some boundary conditions and tests had to be manually 
added to various test suites.

/Bob