[Simh] smallest pdp-11 that can run TECO and sockets(*)?

[Shoppa, Tim]

The later PDP-11 processor handbooks have a decent cross-reference saying what features and quirks are in each processor from the 11/20 through the J11, going into some of corner cases about how various unusual addressing mode combinations/instructions/traps are implemented in each. Also about registers-accessed-as-memory. A few obvious typos.

Further discussion of more esoteric corner cases is probably best documented in the SIMH sources and past discussions here.

The micronotes go into even more detail about various combinations of Q-bus processors and Q-bus backplanes.

There's a very concise table in http://simh.trailing-edge.com/pdf/pdp11_doc.pdf but doesn't really get into the corner cases:

type bus mem MMU? Umap? EIS? FIS? FPP? CIS? 
11/03  Q 64K no no std opt no no 
11/04  U 64K no no no no no no 
11/05  U 64K no no no no no no 
11/20  U 64K no no no no no no 
11/23  Q 4M std no std no opt opt 
11/23+ Q 4M std no std no opt opt 
11/24  U 4M std std std no opt opt 
11/34  U 256K std no std no opt no 
11/40  U 256K std no std opt no no 
11/44  U 4M std std std no opt opt 
11/45  U 256K std no std no opt no 
11/53  Q 4M std no std no std opt 
11/60  U 256K std no std no std no 
11/70  U 4M std std std no opt no 
11/73  Q 4M std no std no std opt 
11/73B Q 4M std no std no std opt 
11/83  Q 4M std no std no std opt 
11/84  U 4M std std std no std opt 
11/93  Q 4M std no std no std opt 
11/94  U 4M std std std no std opt 

Tim.
________________________________________
From: simh-bounces at trailing-edge.com [simh-bounces at trailing-edge.com] on behalf of Andreas Davour [ante at Update.UU.SE]
Sent: Saturday, July 07, 2012 11:41 AM
Cc: simh at trailing-edge.com
Subject: Re: [Simh] smallest pdp-11 that can run TECO and sockets(*)?

Am I the only one that feels all this data belongs in a table of some
sort?

-andreas

--
"economics is a pseudoscience; the astrology of our time"
Kim Stanley Robinson
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