[Simh] Problems with HSA in H316

[Dennis Boone]

I thought the instruction descriptions of DAD, DSB and NRM from the
Prime documentation for their implementation was interesting, so I
retyped them here.

Their INK, OTK and SCA instructions seem to vary in moving 8 bits
between the keys and the A register.

De

> DAD address
  Double Add
  I X 0 1 1 0 1 1 0 0 0 0 0 0 CB\2    (R mode long)
  [ DISPLACEMENT\16 ]

  I X 0 1 1 0 DISPLACEMENT\10         (S, R mode form)

Calculates an effective address, EA.  Fetches the 31-bit contents of
the location specified by EA and adds them to the 31-bit contents of A
and B.  Stores the result in A and B.

If the result is greater than or equal to 2**30, an integer exception
occurs and the instruction loads bit 1 of A with a 1, and bits 2 to 16
of A and bits 2 to 16 of B with (result - (2**30)).  Bit 1 of B
contains 0.

If the result is less than -(2**30), an integer exception occurs and
the instruction loads bit 1 of A with a 0 and bits 2 to 16 of A and
bits 2 to 16 of B with the negative of (result + (2**30)).  Bit 1 of B
contains 0.

If no integer exception occurs, CBIT is reset to 0.  At the end of the
instruction, LINK contains the carry-out bit.  The condition codes
reflect the result of the oepration.  (See Appendix A.)

If an integer exception occurs and bit 8 of the keys contains a 0, the
instruction sets CBIT to 1.  If bit 8 contains a 1, the instruction
sets CBIT to 1 and causes an integer exception fault.  See Chapter 10
of the System Architecture Reference Guide for more information.

> DSB address
  Double Subtract
  I X 0 1 1 1 1 1 0 0 0 0 0 0 CB\2    (R mode long)
  [ DISPLACEMENT\16 ]

  I X 0 1 1 1 DISPLACEMENT\10         (S mode; R mode short)

Calculates an effective address, EA.  Fetches the 31-bit integer
contained in the locations specified by EA and EA+1 and subtracts it
from the 31-bit integer contained in A and B.  Stores the result in A
and B.

If the result is greater than or equal to 2**30, and integer exception
occurs and the DSB instruction loads bit 1 of A with 1, and bits 2 to
16 of A and 2 to 16 of B with the absolute value of (result - (2**30)).
Bit 1 of B must be 0.

If the result is less than -(2**30), an integer exception occurs and
the instruction loads bit 1 of A with a 0, and bits 2 to 16 of A and
bits 2 to 16 of B with the negative of (result + (2**30)).  Bit 1 of B
must be 0.

If no integer exception occurs, CBIT is reset to 0.  At the end of the
instruction, LINK contains the borrow bit.  The condition codes reflect
the result of the operation.  (See Appendix A.)

If an integer exception occurs and bit 8 of the keys contains 0, the
instruction sets CBIT to 1.  If bit 8 contains a 1, the instruction
sets CBIT to 1 and causes an integer exception fault.  See Chapter 10
of the System Architecture Reference Guide for more information.

                                 Notes
                                 -----

    1.  Bit 17 of each 31-bit integer must be 0 or indeterminate
        results occur.

    2.  This instruction executes in double precision mode only.

    3.  To negate a 31-bit integer, subtract if from 0.

> NRM
  Normalize
  0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1     (S, R mode form)

Shifts the 31-bit integer in A and B to the left arithmetically,
shifting in 0s into bit 16 of B.  The shift does not affect bit 1 of B
or bit 1 of A.  The instruction shifts bits out of bit 2 in A until the
value of bit 2 is opposite the value of bit 1 in A.  Loads bits 9-16 of
the S and R mode keys with the number of shifts performed.

Normalizing 0 on all machines results in the following: zeros are
loaded in bits 9-16 of KEYS; bit 1 of the B register is ignored in
the test for zero.  Bit 1 of the B register may be reset or left
unchanged, depending on the processor.

Leaves the values of CBIT and the condition codes unchanged; the value
of LINK is indeterminate.

                                Note
                                ----

    Since the bits shifted out of bit 2 in A contain copies of the
    sign of the 31-bit number, the shift results in no loss of
    information.