[Simh] UNS: Representative Instruction Execution Timing

[Vince Mulhollon]

On Tue, Apr 05, 2011 at 11:09:08AM -0400, Brad Parker wrote:
> It might be confused, but I'd think you could get access
> to the TSC register on most modern cpu's running windows.

TSC doesn't work on any motherboard with multiple processors or any
hyperthreading processors or any processor with power-saving enabled
or any processor that can be hibernated.

Some "recent" intel processors run TSC constant rate rather than
being a instruction counter.  Good for this app, but now you need 
CPU detection code and/or it'll only work on the most recent intel.
On linux google for "constant_tsc".  I would imagine there is also 
a way to do this on legacy OS; OS/2, windows, msdos, etc.

Also AMD does TSC different than intel w/ respect to syncing multiple
cores / hyperthreading.  So intel and AMD boards will have different
behavior if they are both HT and depending on how the OS behaves 
w/ respect to core locking a process under load.  May or may not matter.

TSC can be used at great peril, but it literally either needs separate 
builds per CPU mfgr and CPU family, or it needs some pretty complicated 
steering logic, or it needs a secondary control loop outside the TSC
control loop (probably using wall clock) to self tune the TSC.

Then there's "seccomp mode" sort of a virtualization / secure chroot
kinda thing, which no one uses, which disables TSC, but people keep on 
claiming they'll sandbox their browser into it RSN, etc.  Probably
not relevant but TSC can be messed up by some strange rarely deployed
virtualization technologies, so keep that in mind for bug triage time.

TSC is a "there be dragons" area on the map, although it does technically
exist.