[Simh] pdp11: mmr0 and reset

[Walter F.J. Mueller]

Dear all,

I'm recreating a 11/70 in an FPGA and do a lot of testing lately, running
papertape maindecs and xxdp codes on the FPGA design and also in simh.

The EKBE diagnostic "PDP 11/70 memory management diagnostic" gives the
messages (simh 3.7-3 run with set cpu 11/70 3m):

    MEMORY MANAGEMENT REGISTER 0 WILL NOT CLEAR
    (MMR0)  TESTNO  ERRORPC
    011342  000011  041662
    CAN'T SET 171000 IN MMR0
    (MMR0)  TESTNO  ERRORPC
    171342  000011  041710
    MEMORY MANAGEMENT REGISTER 0 WILL NOT CLEAR
    (MMR0)  TESTNO  ERRORPC
    000342  000011  041730

I used EKBEE1.BIC, but maindec-11-dekbe-b-pb gives similar results.
The test is

   41642:  MOV #177572,R0
   41646:  MOV #171000,(R0)
   41652:  NOP
   41654:  RESET
   41656:  MOV (R0),R1
   41660:  BEQ 41664
   41662:  EMT 7

so it loads 171000 into MMR0, does a RESET, and expect it fully cleared
afterwards. The code for RESET in pdp11_cpu.c is

    case 5:                                     /* RESET */
       if (cm == MD_KER) {
         reset_all (2);                      /* skip CPU, sys reg */
         PIRQ = 0;                           /* clear PIRQ, STKLIM, */
         STKLIM = 0;                         /* MMR0<15:12,0>, */
         for (i = 0; i < IPL_HLVL; i++) int_req[i] = 0;
         MMR0 = MMR0 & ~(MMR0_MME | MMR0_FREEZE);
         MMR3 = 0;                           /* MMR3 */
         trap_req = trap_req & ~TRAP_INT;
         dsenable = calc_ds (cm);
       }

so it explicitely only clears MMR0<15:13,0> (the comment is misleading,
MMR0_FREEZE is 0160000).

simh does not clear the 'trap enable' and 'mem mgt trap' bits.
simh assumes that bits mmr0<6:1> are not writable (MMR0_WR is 0171401).

EKBE obviously expects, that bits mmr0<12,9> are cleared by RESET.
EKBE also expects, that mmr0<6:1> is either writable, or also cleared
by RESET.

So there seems to be a discrepancy between the 11/70 implementation in
simh and what EKBE expects.


			With best regards,	Walter